A low power multi-channel single ramp ADC with up to 3.2 GHz virtual clock

IEEE Transactions on Nuclear Science

Volumn 54, Issue 5, 2007, Pages 1735-1742

  Delagnes, Eric ^a   Breton, Dominique ^b   Lugiez, Francis ^a   Rahmanifard, Reza ^a,c  

^a CEA SACLAY   (France)

^b UNIVERSITÉ PARIS SUD   (France)

^c EASIL ^*  (France)

Author keywords

Analog digital conversion; CMOS; Delay lock loop; Front end electronics; Mixed analog digital integrated circuits; Time measurement

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC POWER UTILIZATION; TIME DELAY; TIME MEASUREMENT; TIMING CIRCUITS;

DELAY LOCK LOOP; FRONT END ELECTRONICS; MIXED ANALOG DIGITAL INTEGRATED CIRCUITS; SPECTROSCOPY MEASUREMENT;

ANALOG TO DIGITAL CONVERSION;

EID: 35348934440     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.906170     Document Type: Article

References (8)

1. O. B. Milgrome, S. A. Kleinfelder, and M. E. Levi, "A 12-bit analog to digital converter for VLSI applications in nuclear science," IEEE Trans. Nucl Sci., vol. 39, no. 4, pp. 771-775, Aug. 1992.
2. O. B. Milgrome and S. A. Kleinfelder, "A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog to digital converter integrated circuit," IEEE Trans. Nucl. Sci., vol. 40, no. 4, pp. 721-723, Aug. 1993.
3. M. S. Emery et al., "A multi-channel ADC for use in the PHENIX detector," IEEETrans. Nucl. Sci., vol. 44, no. 3, pp. 374-378, Jun. 1997.
4. P. Bailly, J. Chauveau, J. F. Genat, J. F. Huppert, H. Lebbolo, L. Roos, and B. Zhang, "A 16-channel digital TDC chip with internal buffering and selective readout for the DIRC Cherenkov counter of the BABAR experiment," Nucl. Instrum. Methods Phys. Res. A, vol. A433, pp. 157-169, 1999.
5. M. Mota and J. Christiansen, "A high-resolution time interpolator based on a DLL and a RC delay line," IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1360-1366, Oct. 1999.
6. E. Delagnes, Y. Degerli, P. Goret, P. Nayman, F. Toussenel, and P. Vincent, "SAM: A new GHz sampling ASIC for the HESS-II front-end electronics," Nucl. Instrum. Methods Phys. Res. A, no. A567, pp. 21-26, 2006.
7. F. Lugiez, Etude Du Bruit d'un Générateur De Rampe Pour un Convertisseur Wilkinson DAPNIA Internal Rep. 07-60 [Online]. Available: http://www-dapnia.cea.fr/Phocea/file.php?class=std&&file=Doc/ Publications/Archives/dapnia-07-60.pdf
8. D. Draxelmayr, "A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS," ISSCC Dig. Tech. Papers, pp. 264-265, Feb. 2004.