CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 3, 2001, Pages 417-423

  Foley, David J ^a,c   Flynn, Michael P ^b,c  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b University Park   (Ireland)

^c IEEE   (United States)

Author keywords

CMOS analog integrated circuits; Delay locked loops; Frequency synthesizers; Tunable oscillators; Voltage controlled oscillators

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; FREQUENCY SYNTHESIZERS; JITTER; VARIABLE FREQUENCY OSCILLATORS;

DELAY LOCKED LOOPS; TUNABLE OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 0035273837     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.910480     Document Type: Article

References (11)

1. PLL/DLL system noise analysis for low-jitter clock synthesizer design
2. An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low jitter
3. A high-resolution time interpolator based on a delay-locked loop and an RC delay line
4. CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature compensated tunable oscillator
5. A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
6. A 2-GHz VCO with process and temperature compensation
7. A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
8. High-speed electrical signaling: Overview and limitations
9. A low-jitter 0.3-165 MHz CMOS PLL synthesizer for 3-V/5-V operation
10. Low-jitter process-independent DLL and PLL based on self-biased techniques
11. A semidigital dual delay-locked loop