Delay25 an ASIC for timing adjustment in LHC

Proceedings - 11th Workshop on Electronics for LHC and Future Experiments, LECC 2005

Volumn , Issue , 2005, Pages 148-152

  Furtado, H ^a   Schrader, J ^a   Marchioro, A ^a   Moreira, P ^a  

^a CERN   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EXPERIMENTS;

CALIBRATION REFERENCE; CMOS TECHNOLOGY; DIGITAL SIGNALS; PROGRAMMABLE DELAY LINES; RADIATION TOLERANT; REFERENCE CLOCK; SUPPLY VOLTAGES; TEMPERATURE VARIATION;

CLOCKS;

EID: 79954619935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. B.G. Taylor, "Timing Distribution at the LHC", Proc. 8th Workshop on Electronics for LHC Experiments,? Colmar, France, 9-13 September 2002, CERN 2002-003, pp. 63-74.
2. T. Toifl, R. Vari, ?A 4-Channels Rad-Hard Delay Generator ASIC with 1ns minimum time step for LHC experiments?, Fourth Workshop on Electronics for LHC Experiments.
3. G. Anelli, M. Campbell, M. Delmastro, F. Faccio, S. Florian, A. Giraldo, E. Heijne, P. Jarron, K. Kloukinas, A. Marchioro, P. Moreira, and W. Snoeys, ?Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects?, IEEE Trans. Nuclear Sciences. Vol. 46 No.6, p.1690, 1999.
4. Christiansen, J., An integrated high-resolution CMOS timing generator based on an array of Delay Locked Loops, IEEE Journal of Solid-State Circuits, Vol.31, No.7, pp. 952-957, Jul. 96.
5. M. Mota, ? Design and Characterization of CMOS High-Resolution Time-to-Digital Converters ?, Ph.D. Thesis at the UNIVERSIDADE T?CNICA DE LISBOA INSTITUTO SUPERIOR T?CNICO, Portugal, October 2000
6. Kim, L. et al., Metastability of CMOS latch/flip-flop, IEEE Journal of Solid-State Circuits, Vol. 25, No. 4, pp. 942-951, Aug. 90.