A low-power small-area ± 7.28-ps-Jitter 1-GHz DLL-based clock generator

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1414-1420

  Kim, Chulwoo ^a   Hwang, In Chul ^b   Kang, Sung Mo Steve ^c  

^a IBM MICROELECTRONICS   (United States)

^b SAMSUNG Electronics   (South Korea)

^c University of California Santa Cruz   (United States)

Author keywords

Clock generator; Delay locked loops (DLLs); Frequency multiplication; Limited locking range; Low jitter; Phase detector (PD)

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; JITTER; PHASE LOCKED LOOPS;

CLOCK GENERATOR; DELAY LOCKED LOOPS; PHASE DETECTOR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036858568     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803936     Document Type: Article

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