An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 149-152

  Edward Lee, M J ^a   Dally, W J ^a   Poulton, J W ^a   Chiang, P ^a   Greenwood, S F ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; JITTER; TELECOMMUNICATION LINKS;

CLOCK AND DATA RECOVERY (CDR) CIRCUITS; SERIAL LINKS;

NONBIBLIOGRAPHIC RETRIEVAL SYSTEMS;

EID: 0034798939     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Transmitter equalization for 4Gb/s signaling
2. Low-power area efficient high speed I/O circuit techniques
3. A semidigital dual delay-locked loop
4. An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
5. A variable-frequency parallel I/O interface with adaptive power-supply regulation