RAFT: A router architecture with frequency tuning for on-chip networks

Journal of Parallel and Distributed Computing

Volumn 71, Issue 5, 2011, Pages 625-640

  Mishra, Asit K ^a   Yanamandra, Aditya ^a   Das, Reetuparna ^a   Eachempati, Soumya ^a   Iyer, Ravi ^b   Vijaykrishnan, N ^a   Das, Chita R ^a  

^a The Pennsylvania State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Chip multiprocessors; Congestion management; DVFS; Network on chips; On chip router; Performance; Power; Reliability

Indexed keywords

CHIP MULTIPROCESSOR; CONGESTION MANAGEMENT; DVFS; NETWORK-ON-CHIPS; ON CHIPS; PERFORMANCE; POWER;

BENCHMARKING; COMPUTER ARCHITECTURE; ENERGY MANAGEMENT; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; NETWORK MANAGEMENT; OPTIMIZATION; RELIABILITY ANALYSIS;

ROUTERS;

EID: 79953202138     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2010.09.005     Document Type: Article

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