Performance and power optimization through data compression in network-on-chip architectures

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2008, Pages 215-225

  Das, Reetuparna ^a   Mishra, Asit K ^a   Nicopoulosd, Chrysostomos ^a   Park, Dongkook ^a   Narayanan, Vijaykrishnan ^a   Iyer, Ravishankar ^b   Yousif, Mazin S ^b   Das, Chita R ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; COMPUTER ARCHITECTURE; COMPUTER NETWORKS; COMPUTERS; ELECTRIC NETWORK TOPOLOGY; FABRICS; ROUTERS; SECURITY OF DATA;

COMMUNICATION LATENCIES; MICROARCHITECTURES; MULTICORE ARCHITECTURES; NETWORK LATENCIES; NETWORK ON CHIPS; NOC ARCHITECTURES; NON UNIFORMS; ON CHIPS; PERFORMANCE BENEFITS; POWER CONSUMPTIONS; POWER OPTIMIZATIONS; POWER SAVINGS; ROUTER ARCHITECTURES; SIMULATION RESULTS;

DATA COMPRESSION;

EID: 57749169508     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2008.4658641     Document Type: Conference Paper

References (37)

1. International Technology Roadmap for Semiconductors (ITRS), 2005 edition, http://www.itrs.net/.
2. TPC-W , http://cs.nyu.edu/totok/ professional/ software/tpcw/tpcw.html.
3. MediaBench II,http://euler.slu.edu/ fritts/mediabench/.
4. A. R. Alameldeen and D. A. Wood. Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches. Technical Report 1500, Computer Sciences Department, University of Wisconsin-Madison,April2004.
5. A. R. Alameldeen and D. A.Wood. Adaptive cache compression for high-performance processors. In ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture, page 212, 2004.
6. A. R. Alameldeen and D. A. Wood. Interactions between compression and prefetching in chip multiprocessors. In HPCA '07: Proceedings of the 13th International Symposium on High-Performance Computer Architecture, pages 228-239, 2007.
7. P. Barford and M. Crovella. Generating representative web workloads for network and server performance evaluation. In SIGMETRICS '98/PERFORMANCE '98: Proceedings of the 1998 ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems, pages 151-160, 1998.
8. B. M. Beckmann and D. A. Wood. Managing wire delay in large chip-multiprocessor caches. In MICRO 37: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, pages 319-330, 2004.
9. S. Borkar. Design challenges of technology scaling. IEEE Micro, 19(4):23-29, 1999.
10. R. Canal, A. González, and J. E. Smith. Very low power pipelines using significance compression. In MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, pages 181-190, 2000.
11. W. J. Dally and B. Towles. Route packets, not wires: On-chip inteconnection networks. In DAC '01: Proceedings of the 38th Conference on Design Automation, pages 684-689, 2001.
12. N. Eisley, L.-S. Peh, and L. Shang. In-network cache coherence. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pages 321-332, 2006.
13. M. Farrens and A. Park. Dynamic base register caching: a technique for reducing address bus width. In ISCA '91: Proceedings of the 18th Annual International Symposium on Computer Architecture, pages 128-137, 1991.
14. M. Galles. Scalable pipelined interconnect for distributed endpoint routing: the sgi spider chip. In Symposium on High Performance Interconnects (Hot Interconnects), pages 141-146, 1996.
15. A. Gonzlez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In ICS '95: Proceedings of the 9th International Conference on Supercomputing, pages 338-347, 1995.
16. T. L. Johnson, 1998. Run-Time Adaptive Cache Management, PhD Thesis, University of Illinois,Urbana,IL.
17. K. Kant and R. Iyer. Compressibility characteristics of address/data transfers in commercial workloads. In Proceedings of the Fifth Workshop on Computer Architecture Evaluation Using Commercial Workloads, pages 59-67, 2002.
18. K. Kant and R. Iyer. Design and performance of compressed interconnects for high performance servers. In ICCD '03: Proceedings of the 21st International Conference on Computer Design, page 164, 2003.
19. J. Kim, C. Nicopoulos, and D. Park. A gracefully degrading and energy-efficient modular router architecture for on-chip networks. In ISCA '06: Proceedings of the 33rd Annual International Symposium on Computer Architecture, pages 4-15, 2006.
20. M. Kjelso, M. Gooch, and S. Jones. Design and performance of a main memory hardware data compressor. In 22nd EUROMICRO Conference, pages 423-430, 1996.
21. R. Kumar, V. Zyuban, and D. M. Tullsen. Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling. SIGARCH Comput. Archit. News, 33(2):408-419, 2005.
22. S. Kumar and C. Wilkerson. Exploiting spatial locality in data caches using spatial footprints. In ISCA '98: Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 357-368, 1998.
23. J.-S. Lee, W.-K. Hong, and S.-D. Kim. Design and evaluation of a selective compressed memory system. In ICCD '99: Proceedings of the 1999 IEEE International Conference on Computer Design, page 184, 1999.
24. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir. Design and management of 3d chip multiprocessors using network-in-memory. In ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture, pages 130-141, 2006.
25. P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A full system simulation platform. Computer, 35(2):50-58, 2002.
26. R. Mullins, A.West, and S. Moore. Low-latency virtual-channel routers for on-chip networks. In ISCA '04: Proceedings of the 31st Annual International Symposium on Computer Architecture, page 188, 2004.
27. R. Mullins, A. West, and S. Moore. The design and implementation of a low-latency on-chip network. In ASP-DAC '06: Proceedings of the 2006 conference on Asia South Pacific design automation, pages 164-169, 2006.
28. N. Muralimanohar and R. Balasubramonian. Interconnect design considerations for large nuca caches. ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture, pages 369-380, 2007.
29. D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C. R. Das. Exploring fault-tolerant network-on-chip architectures. In DSN '06: Proceedings of the International Conference on Dependable Systems and Networks (DSN'06), pages 93-104, 2006.
30. L.-S. Peh and W. J. Dally. A delay model and speculative architecture for pipelined routers. In HPCA '01: Proceedings of the 7th International Symposium on High-Performance Computer Architecture, page 255, 2001.
31. L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha. Thermal modeling, characterization and management of on-chip networks. In MICRO 37: Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture, pages 67-78, 2004.
32. D. Tarjan, S. Thoziyoor, and N. P. Jouppi. CACTI 4.0. Technical Report,HPL-2006-86,June 2006.
33. R. B. Tremaine, T. B. Smith, M.Wazlowski, D. Har, K.-K. Mak, and S. Arramreddy. Pinnacle: Ibm mxt in a memory controller chip. IEEE Micro, 21(2):56-68, 2001.
34. A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In ICS '99: Proceedings of the 13th International Conference on Supercomputing, pages 145-154, 1999.
35. H. Wang, L.-S. Peh, and S. Malik. Power-driven design of router microarchitectures in on-chip networks. In MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, page 105, 2003.
36. J. Yang, R. Gupta, and C. Zhang. Frequent value encoding for low power data buses. ACM Trans. Des. Autom. Electron. Syst., pages 354-384, 2004.
37. Y. Zhang, J. Yang, and R. Gupta. Frequent value locality and value-centric data cache design. In ASPLOS-IX: Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating systems, pages 150-159, 2000.