Impact of Dynamic Voltage Frequency Scaling on the Architectural Vulnerability of GALS architectures

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 351-356

  Soundararajan, Niranjan ^a   Vijaykrishnan, N ^a   Sivasubramaniam, Anand ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

Microarchitecture; Multi clocked domains; Soft errors

Indexed keywords

ALGORITHMS; ERROR DETECTION; ERRORS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; PIPELINES; POWER ELECTRONICS; RELIABILITY;

ARCHITECTURAL LEVELS; GALS ARCHITECTURES; MICROARCHITECTURE; MULTI-CLOCKED DOMAINS; PIPELINE STRUCTURES; RELIABILITY IMPACTS; SIGNIFICANT IMPACTS; SOFT ERROR MASKING; SOFT ERRORS; TECHNOLOGY SCALING;

ERROR CORRECTION;

EID: 57549104723     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1394016     Document Type: Conference Paper

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