A holistic approach to designing energy-efficient cluster interconnects

IEEE Transactions on Computers

Volumn 54, Issue 6, 2005, Pages 660-671

  Kim, Eun Jung ^a   Link, Greg M ^b   Yum, Ki Hwan ^c   Vijaykrishnan, N ^b   Kandemir, Mahmut ^b   Irwin, Mary J ^b   Das, Chita R ^b  

^a Texas AandM University   (United States)

^b The Pennsylvania State University   (United States)

^c UNIVERSITY OF TEXAS AT SAN ANTONIO   (United States)

Author keywords

Buffer design; Cluster interconnect; Dynamic link shutdown; Dynamic voltage scaling; Energy optimization; Link design; Switch design

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DESIGN; ELECTRIC POTENTIAL; INTERFACES (COMPUTER); LEAKAGE CURRENTS; OPTIMIZATION;

BUFFER DESIGN; CLUSTER INTERCONNECT; DYNAMIC LINK SHUTDOWN; DYNAMIC VOLTAGE SCALING; ENERGY OPTIMIZATION; LINK DESIGN; NETWORK INTERFACE CARD; SWITCH DESIGN;

INTERCONNECTION NETWORKS;

EID: 21044433763     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.86     Document Type: Article

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