-
1
-
-
0242612078
-
Energy management for real-time embedded applications with compiler support
-
ACM, New York
-
ABOUGHAZALEH, N., CHILDERS, B., MOSSE, D., MELHEM, R., AND CRAVEN, M. 2003. Energy management for real-time embedded applications with compiler support. In Proceedings of the Conference on Language, Compiler, and Tool Support for Embedded Systems. ACM, New York.
-
(2003)
Proceedings of the Conference on Language, Compiler, and Tool Support for Embedded Systems
-
-
Aboughazaleh, N.1
Childers, B.2
Mosse, D.3
Melhem, R.4
Craven, M.5
-
2
-
-
0038674055
-
Toward the placement of power management points in real time applications
-
ACM, New York
-
ABOUGHAZALEH, N.,MOSSE, D., CHILDERS, B., AND MELHEM, R. 2001. Toward the placement of power management points in real time applications. In Proceedings of the Workshop on Compilers and Operating Systems for Low-Power. ACM, New York.
-
(2001)
Proceedings of the Workshop on Compilers and Operating Systems for Low-power
-
-
Aboughazaleh, N.1
Mosse, D.2
Childers, B.3
Melhem, R.4
-
3
-
-
84884185725
-
Collaborative operating system and compiler power management for real-time applications
-
IEEE, Los Alamitos, CA
-
ABOUGHAZALEH, N.,MOSSE, D., CHILDERS, B.,MELHEM, R., AND CRAVEN, M. 2003. Collaborative operating system and compiler power management for real-time applications. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA.
-
(2003)
Proceedings of the Real-time Embedded Technology and Applications Symposium
-
-
Aboughazaleh, N.1
Mosse, D.2
Childers, B.3
Melhem, R.4
Craven, M.5
-
4
-
-
0004072686
-
-
Addison-Wesley, Upper Saddle River, NJ
-
AHO, A. V.,SETHI, R., ANDULLMAN, J. D. 1986. Compilers - Principles, Techniques, and Tools. Addison-Wesley, Upper Saddle River, NJ.
-
(1986)
Compilers - Principles, Techniques, and Tools
-
-
Aho, V.1
Sethi, A.R.2
Andullman, J.D.3
-
6
-
-
0038345691
-
Virtual simple architecture (VISA): Exceeding the complexity limit in safe real-time systems
-
ACM, New York
-
ANANTARAMAN, A., SETH, K., PATIL, K., ROTENBERG, E., AND MUELLER, F. 2003. Virtual simple architecture (VISA): Exceeding the complexity limit in safe real-time systems. In Proceedings of the International Symposium on Computer Architecture. ACM, New York, 250-261.
-
(2003)
Proceedings of the International Symposium on Computer Architecture
, pp. 250-261
-
-
Anantaraman, A.1
Seth, K.2
Patil, K.3
Rotenberg, E.4
Mueller, F.5
-
7
-
-
21644456004
-
Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (visa)
-
IEEE, Los Alamitos, CA
-
ANANTARAMAN, A., SETH, K., PATIL, K., ROTENBERG, E., AND MUELLER, F. 2004. Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (visa). In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 114-125.
-
(2004)
Proceedings of the Real-time Systems Symposium
, pp. 114-125
-
-
Anantaraman, A.1
Seth, K.2
Patil, K.3
Rotenberg, E.4
Mueller, F.5
-
8
-
-
84882618546
-
Bounding worst-case instruction cache performance
-
IEEE, Los Alamitos, CA
-
ARNOLD, R.,MUELLER, F.,WHALLEY, D. B., AND HARMON, M. 1994. Bounding worst-case instruction cache performance. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 172-181.
-
(1994)
Proceedings of the Real-time Systems Symposium
, pp. 172-181
-
-
Arnold, R.1
Mueller, F.2
Whalley, D.B.3
Harmon, M.4
-
9
-
-
0035680483
-
Dynamic and aggressive scheduling techniques for power-aware real-time systems
-
IEEE, Los Alamitos, CA
-
AYDIN, H., MELHEM, R., MOSSE, D., AND MEJIA-ALVAREZ, P. 2001. Dynamic and aggressive scheduling techniques for power-aware real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(2001)
Proceedings of the Real-time Systems Symposium
-
-
Aydin, H.1
Melhem, R.2
Mosse, D.3
Mejia-Alvarez, P.4
-
12
-
-
0036994494
-
WCET analysis of probabilistic hard real-time systems
-
IEEE, Los Alamitos, CA
-
BERNAT, G., COLIN, A., AND PETTERS, S. 2002. WCET analysis of probabilistic hard real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(2002)
Proceedings of the Real-time Systems Symposium
-
-
Bernat, G.1
Colin, A.2
Petters, S.3
-
13
-
-
0033719421
-
Watch: A framework for architectural-level power analysis and optimizations
-
IEEE, Los Alamitos, CA
-
BROOKS, D.,TIWARI, V., ANDMARTONOSI,M. 2000. Watch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture. IEEE, Los Alamitos, CA, 83-94.
-
(2000)
Proceedings of the 27th Annual International Symposium on Computer Architecture
, pp. 83-94
-
-
Brooks, D.1
Tiwari, V.2
Andmartonosi, M.3
-
14
-
-
0003510233
-
-
Tech. rep. CS-TR-96-1308, University of Wisconsin
-
BURGER, D.,AUSTIN, T., ANDBENNETT, S. 1996. Evaluating future microprocessors: The simplescalar toolset. Tech. rep. CS-TR-96-1308, University of Wisconsin.
-
(1996)
Evaluating Future Microprocessors: The Simplescalar Toolset
-
-
Burger, D.1
Austin, T.2
Andbennett, S.3
-
15
-
-
33746036204
-
Applying static WCET analysis to automotive communication software
-
IEEE, Los Alamitos, CA
-
BYHLIN, S., ERMEDAHL, A., GUSTAFSSON, J., AND PER, B. L. 2005. Applying static WCET analysis to automotive communication software. In Proceedings of the Euromicro Conference on Real-Time Systems. IEEE, Los Alamitos, CA.
-
(2005)
Proceedings of the Euromicro Conference on Real-time Systems
-
-
Byhlin, S.1
Ermedahl, A.2
Gustafsson, J.3
Per, B.L.4
-
16
-
-
84944317742
-
-
C-LAB. Wcet benchmarks. http://www.c-lab.de/home/en/download.html.
-
Wcet Benchmarks
-
-
-
17
-
-
0030244313
-
Combining static worst-case timing analysis and program proof
-
CHAPMAN, R., BURNS, A., AND WELLINGS, A. 1996. Combining static worst-case timing analysis and program proof. Real-Time Syst. 11, 2, 145-171.
-
(1996)
Real-time Syst
, vol.11
, Issue.2
, pp. 145-171
-
-
Chapman, R.1
Burns, A.2
Wellings, A.3
-
18
-
-
0034794870
-
Retargetable static-timing analysis for embedded software
-
IEEE, Los Alamitos, CA
-
CHEN, K.,MALIK, S., AND AUGUST,D. I. 2001. Retargetable static-timing analysis for embedded software. In Proceedings of the International Symposium on System Synthesis. IEEE, Los Alamitos, CA.
-
(2001)
Proceedings of the International Symposium on System Synthesis
-
-
Chen, K.1
Malik, S.2
Augustd., I.3
-
19
-
-
0033733125
-
Worst-case execution time analysis for a processor with branch prediction
-
COLIN, A. AND PUAUT, I. 2001. Worst-case execution time analysis for a processor with branch prediction. Real-Time Syst. 18, 2/3, 249-174.
-
(2001)
Real-time Syst
, vol.18
, Issue.2-3
, pp. 249-174
-
-
Colin, A.1
Puaut, I.2
-
21
-
-
12344284984
-
Execution-time analysis for embedded real-time systems
-
ENGBLOM, J.,ERMEDAHL, A., SJDIN, M.,GUSTAFSSON, J., AND HANSSON, H. 2001. Execution-time analysis for embedded real-time systems. Int. J. Softw. Tools Technol. Trans.
-
(2001)
Int. J. Softw. Tools Technol. Trans
-
-
Engblom, J.1
Ermedahl, A.2
Sjdin, M.3
Gustafsson, J.4
Hansson, H.5
-
22
-
-
0033334995
-
Efficient and precise cache behavior prediction for real-time systems
-
FERDINAND, C. ANDWILHELM, R. 1999. Efficient and precise cache behavior prediction for real-time systems. Real-Time Syst. 17, 2/3, 131-181.
-
(1999)
Real-time Syst
, vol.17
, Issue.2-3
, pp. 131-181
-
-
Ferdinand, C.1
Andwilhelm, R.2
-
23
-
-
27944488327
-
Automatic scenario detection for improved WCET estimation
-
ACM, New York
-
GHEORGHITA, V. S., STUIJK, S., BASTEN, T., AND CORPORAAL, H. 2005. Automatic scenario detection for improved WCET estimation. In Proceedings of the Design Automation Conference. ACM, New York.
-
(2005)
Proceedings of the Design Automation Conference
-
-
Gheorghita, V.S.1
Stuijk, S.2
Basten, T.3
Corporaal, H.4
-
24
-
-
0029457297
-
Comparing algorithms for dynamic speed-setting of a low-power cpu
-
ACM, New York
-
GOVIL, K., CHAN, E., AND WASSERMAN, H. 1995. Comparing algorithms for dynamic speed-setting of a low-power cpu. In Proceedings of the 1st International Conference on Mobile Computing and Networking. ACM, New York.
-
(1995)
Proceedings of the 1st International Conference on Mobile Computing and Networking
-
-
Govil, K.1
Chan, E.2
Wasserman, H.3
-
26
-
-
85018376784
-
Policies for dynamic clock scheduling
-
USENIX, Berkeley, CA
-
GRUNWALD, D., LEVIS, P., III, C. M., NEUFELD, M., AND FARKAS, K. 2000. Policies for dynamic clock scheduling. In Proceedings of the Symposium on Operating Systems Design and Implementation. USENIX, Berkeley, CA.
-
(2000)
Proceedings of the Symposium on Operating Systems Design and Implementation
-
-
Grunwald, D.1
Levis, P.2
Iii, C.M.3
Neufeld, M.4
Farkas, K.5
-
27
-
-
84880876231
-
A retargetable technique for predicting execution time
-
IEEE, Los Alamitos, CA
-
HARMON, M., BAKER, T. P., AND WHALLEY, D. B. 1992. A retargetable technique for predicting execution time. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 68-77.
-
(1992)
Proceedings of the Real-time Systems Symposium
, pp. 68-77
-
-
Harmon, M.1
Baker, T.P.2
Whalley, D.B.3
-
28
-
-
0343341629
-
Supporting timing analysis by automatic bounding of loop iterations
-
HEALY, C., SJODIN, M., RUSTAGI, V., WHALLEY, D., AND VAN ENGELEN, R. 2000. Supporting timing analysis by automatic bounding of loop iterations. Real-Time Syst. 18, 2/3, 121-148.
-
(2000)
Real-time Syst
, vol.18
, Issue.2-3
, pp. 121-148
-
-
Healy, C.1
Sjodin, M.2
Rustagi, V.3
Whalley, D.4
Van Engelen, R.5
-
29
-
-
0032713797
-
Bounding pipeline and instruction cache performance
-
HEALY, C. A., ARNOLD, R. D., MUELLER, F.,WHALLEY, D., AND HARMON,M. G. 1999. Bounding pipeline and instruction cache performance. IEEE Trans. Comput. 48, 1, 53-70.
-
(1999)
Trans. Comput.
, vol.48
, Issue.1
, pp. 53-70
-
-
Healy, C.A.1
Arnold, R.D.2
Mueller, F.3
Whalley, D.4
Harmonm., G.5
-
30
-
-
0031644971
-
Bounding loop iterations for timing analysis
-
IEEE, Los Alamitos, CA
-
HEALY, C. A., SJ ÖDIN, M., AND WHALLEY, D. B. 1998. Bounding loop iterations for timing analysis. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA, 12-21.
-
(1998)
Proceedings of the Real-time Embedded Technology and Applications Symposium
, pp. 12-21
-
-
Healy, C.A.1
Ödin, M.S.J.2
Whalley, D.B.3
-
31
-
-
0029517739
-
Integrating the timing analysis of pipelining and instruction caching
-
IEEE, Los Alamitos, CA
-
HEALY, C. A.,WHALLEY, D. B., AND HARMON, M. G. 1995. Integrating the timing analysis of pipelining and instruction caching. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 288-297.
-
(1995)
Proceedings of the Real-time Systems Symposium
, pp. 288-297
-
-
Healy, C.A.1
Whalley, D.B.2
Harmon, M.G.3
-
32
-
-
84893686212
-
Static-timing analysis of embedded software on advanced processor architectures
-
IEEE, Los Alamitos, CA
-
HERGENHAN, A. AND ROSENSTIEL, W. 2000. Static-timing analysis of embedded software on advanced processor architectures. In Proceedings of the Design Automation Test in Europe. IEEE, Los Alamitos, CA, 552-559.
-
(2000)
Proceedings of the Design Automation Test in Europe
, pp. 552-559
-
-
Hergenhan, A.1
Rosenstiel, W.2
-
33
-
-
27944494362
-
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems
-
IEEE, Los Alamitos, CA
-
JEJURIKAR, R. AND GUPTA, R. 2005. Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. In Proceedings of the Design Automation Conference. IEEE, Los Alamitos, CA.
-
(2005)
Proceedings of the Design Automation Conference
-
-
Jejurikar, R.1
Gupta, R.2
-
34
-
-
4444368993
-
Leakage aware dynamic voltage scaling for realtime embedded systems
-
IEEE, Los Alamitos, CA
-
JEJURIKAR, R., PEREIRA, C., AND GUPTA, R. 2004. Leakage aware dynamic voltage scaling for realtime embedded systems. In Proceedings of the Design Automation Conference. IEEE, Los Alamitos, CA.
-
(2004)
Proceedings of the Design Automation Conference
-
-
Jejurikar, R.1
Pereira, C.2
Gupta, R.3
-
35
-
-
0036997038
-
A fast resource synthesis technique for energy-efficient real-time systems
-
IEEE, Los Alamitos, CA
-
KANG, D., CRAGO, S., AND SUH, J. 2002. A fast resource synthesis technique for energy-efficient real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(2002)
Proceedings of the Real-time Systems Symposium
-
-
Kang, D.1
Crago, S.2
Suh, J.3
-
36
-
-
0030412018
-
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
-
IEEE, Los Alamitos, CA
-
LEE, C., HAHN, J., SEO, Y.,MIN, S., HA, R., HONG, S., PARK, C., LEE, M., AND KIM, C. 1996. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(1996)
Proceedings of the Real-time Systems Symposium
-
-
Lee, C.1
Hahn, J.2
Seo, Y.3
Min, S.4
Ha, R.5
Hong, S.6
Park, C.7
Lee, M.8
Kim, C.9
-
38
-
-
0038682021
-
Voltage-clock scaling for low-energy consumption in fixedpriority real-time systems
-
LEE, Y.-H. AND KRISHNA, C. M. 2003. Voltage-clock scaling for low-energy consumption in fixedpriority real-time systems. Real-Time Syst. 24, 3, 303-317.
-
(2003)
Real-time Syst
, vol.24
, Issue.3
, pp. 303-317
-
-
Lee, Y.-H.1
Krishna, C.M.2
-
39
-
-
0030414718
-
Cache modeling for real-time software: Beyond direct mapped instruction caches
-
IEEE, Los Alamitos, CA
-
LI, Y.-T. S., MALIK, S., AND WOLFE, A. 1996. Cache modeling for real-time software: Beyond direct mapped instruction caches. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 254-263.
-
(1996)
Proceedings of the Real-time Systems Symposium
, pp. 254-263
-
-
Y, -T.S.L.I.1
Malik, S.2
Wolfe, A.3
-
40
-
-
84882634952
-
An accurate worst case timing analysis for RISC processors
-
IEEE, Los Alamitos, CA
-
LIM, S.-S., BAE, Y. H., JANG, G. T., RHEE, B.-D., MIN, S. L., PARK, C. Y., SHIN, H., AND KIM, C. S. 1994. An accurate worst case timing analysis for RISC processors. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 97-108.
-
(1994)
Proceedings of the Real-time Systems Symposium
, pp. 97-108
-
-
Lim, S.-S.1
Bae, Y.H.2
Jang, G.T.3
Rhee, B.-D.4
Min, S.L.5
Park, C.Y.6
Shin, H.7
Kim, C.S.8
-
42
-
-
84974687699
-
Scheduling algorithms for multiprogramming in a hard-real-time environment
-
LIU, C. AND LAYLAND, J. 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. Assoc. Comput. Mach. 20, 1, 46-61.
-
(1973)
J. Assoc. Comput. Mach
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.1
Layland, J.2
-
45
-
-
0030679977
-
Static timing analysis of embedded software
-
ACM, New York
-
MALIK, S.,MARTONOSI, M., AND LI, Y.-T. S. 1997. Static timing analysis of embedded software. In Proceedings of the 34th Conference on Design Automation. ACM, New York, 147-152.
-
(1997)
Proceedings of the 34th Conference on Design Automation
, pp. 147-152
-
-
Malik, S.1
Martonosi, M.2
Li, Y.-T.S.3
-
47
-
-
84879352073
-
Para-scale: Exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling
-
IEEE, Los Alamitos, CA
-
MOHAN, S., MUELLER, F., HAWKINS, W., ROOT, M., HEALY, C., AND WHALLEY, D. 2005. Para-scale: Exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 233-242.
-
(2005)
Proceedings of the Real-time Systems Symposium
, pp. 233-242
-
-
Mohan, S.1
Mueller, F.2
Hawkins, W.3
Root, M.4
Healy, C.5
Whalley, D.6
-
48
-
-
0041571970
-
Compiler-assisted dynamic power-aware scheduling for real-time applications
-
ACM, New York
-
MOSSE, D.,AYDIN, H.,CHILDERS, B., ANDMELHEM, R. 2000. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Proceedings of the Workshop on Compilers and Operating Systems for Low-Power. ACM, New York.
-
(2000)
Proceedings of the Workshop on Compilers and Operating Systems for Low-Power
-
-
Mosse, D.1
Aydin, H.2
Childers, B.3
Andmelhem, R.4
-
49
-
-
0033732401
-
Timing analysis for instruction caches
-
MUELLER, F. 2000. Timing analysis for instruction caches. Real-Time Syst. 18, 2/3, 209-239.
-
(2000)
Real-time Syst
, vol.18
, Issue.2-3
, pp. 209-239
-
-
Mueller, F.1
-
50
-
-
0027556297
-
Predicting program execution times by analyzing static and dynamic program paths
-
PARK, C. Y. 1993. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Syst. 5, 1, 31-61.
-
(1993)
Real-time Syst
, vol.5
, Issue.1
, pp. 31-61
-
-
Park, C.Y.1
-
51
-
-
78751529837
-
The simulation of dynamic voltage scaling algorithms
-
ACM, New York
-
PERING, T., BURD, T., AND BRODERSEN, R. 1995. The simulation of dynamic voltage scaling algorithms. In Proceedings of the Symposium on Low-Power Electronics. ACM, New York.
-
(1995)
Proceedings of the Symposium on Low-Power Electronics
-
-
Pering, T.1
Burd, T.2
Brodersen, R.3
-
53
-
-
0000039023
-
Calculating the maximum execution time of real-time programs
-
PUSCHNER, P. AND KOZA, C. 1989. Calculating the maximum execution time of real-time programs. Real-Time Syst. 1, 2, 159-176.
-
(1989)
Real-time Syst
, vol.1
, Issue.2
, pp. 159-176
-
-
Puschner, P.1
Koza, C.2
-
54
-
-
33749646825
-
Bounding preemption delay within data cache reference patterns for real-time tasks
-
IEEE, Los Alamitos, CA
-
RAMAPRASAD, H. AND MUELLER, F. 2006. Bounding preemption delay within data cache reference patterns for real-time tasks. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA, 71-80.
-
(2006)
Proceedings of the Real-time Embedded Technology and Applications Symposium
, pp. 71-80
-
-
Ramaprasad, H.1
Mueller, F.2
-
56
-
-
0034470880
-
Cache and pipeline sensitive fixed priority scheduling for preemptive realtime systems
-
IEEE, Los Alamitos, CA
-
SCHNEIDER, J. 2000. Cache and pipeline sensitive fixed priority scheduling for preemptive realtime systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 195-204.
-
(2000)
Proceedings of the Real-time Systems Symposium
, pp. 195-204
-
-
Schneider, J.1
-
57
-
-
0348195821
-
Fast: Frequency-aware static timing analysis
-
IEEE, Los Alamitos, CA
-
SETH, K., ANANTARAMAN, A., MUELLER, F., AND ROTENBERG, E. 2003. Fast: Frequency-aware static timing analysis. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA, 40-51.
-
(2003)
Proceedings of the Real-time Systems Symposium
, pp. 40-51
-
-
Seth, K.1
Anantaraman, A.2
Mueller, F.3
Rotenberg, E.4
-
58
-
-
0035279683
-
Intra-task voltage scheduling for low-energy hard real-time applications
-
IEEE, Los Alamitos, CA
-
SHIN, D., KIM, J., AND LEE, S. 2001. Intra-task voltage scheduling for low-energy hard real-time applications. In Proceedings of the Design and Test of Computers. IEEE, Los Alamitos, CA.
-
(2001)
Proceedings of the Design and Test of Computers
-
-
Shin, D.1
Kim, J.2
Lee, S.3
-
59
-
-
0034483995
-
Power optimization of real-time embedded systems on variable speed processors
-
IEEE, Los Alamitos, CA
-
SHIN, Y., CHOI, K., AND SAKURAI, T. 2000. Power optimization of real-time embedded systems on variable speed processors. In Proceedings of the International Conference on Computer-Aided Design. IEEE, Los Alamitos, CA.
-
(2000)
Proceedings of the International Conference on Computer-Aided Design
-
-
Shin, Y.1
Choi, K.2
Sakurai, T.3
-
61
-
-
33749059169
-
Scheduling analysis of real-time systems with precise modeling of cache related preemption delay
-
IEEE, Los Alamitos, CA
-
STASCHULAT, J., SCHLIECKER, S., AND ERNST, R. 2005. Scheduling analysis of real-time systems with precise modeling of cache related preemption delay. In Proceedings of the Euromicro Conference on Real-Time Systems. IEEE, Los Alamitos, CA.
-
(2005)
Proceedings of the Euromicro Conference on Real-time Systems
-
-
Staschulat, J.1
Schliecker, S.2
Ernst, R.3
-
62
-
-
1542330092
-
An abstract interpretation-based timing validation of hard real-time avionics
-
IEEE, Los Alamitos, CA
-
THESING, S., SOUYRIS, J., HECKMANN, R., AND M. LANGENBACH, F. R.,WILHELM, R., AND FERDINAND, C. 2003. An abstract interpretation-based timing validation of hard real-time avionics. In Proceedings of the International Performance and Dependability Symposium. IEEE, Los Alamitos, CA.
-
(2003)
Proceedings of the International Performance and Dependability Symposium
-
-
Thesing, S.1
Souyris, J.2
Heckmann, R.3
Langenbach, F.R.M.4
Wilhelm, R.5
Ferdinand, C.6
-
63
-
-
0039488519
-
Handling irreducible loops: Optimized node splitting vs. djgraphs
-
UNGER, S. AND MUELLER, F. 2002. Handling irreducible loops: Optimized node splitting vs. djgraphs. ACM Trans. Program. Lang. Syst. 24, 4, 299-333.
-
(2002)
ACM Trans. Program. Lang. Syst.
, vol.24
, Issue.4
, pp. 299-333
-
-
Unger, S.1
Mueller, F.2
-
64
-
-
0346935130
-
Data-caches in multitasking hard real-time systems
-
IEEE, Los Alamitos, CA
-
VERA, X., LISPER, B., AND XUE, J. 2003. Data-caches in multitasking hard real-time systems. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(2003)
Proceedings of the Real-time Systems Symposium
-
-
Vera, X.1
Lisper, B.2
Xue, J.3
-
65
-
-
17244380810
-
Parametric timing analysis
-
VIVANCOS, E.,HEALY, C.,MUELLER, F., AND WHALLEY, D. 2001. Parametric timing analysis. In Workshop on Language, Compiler, and Tool Support for Embedded Systems. ACM SIGPLAN Not. 36, 88-93.
-
(2001)
Workshop on Language, Compiler, and Tool Support for Embedded Systems. ACM SIGPLAN Not.
, vol.36
, pp. 88-93
-
-
Vivancos, E.1
Healy, C.2
Mueller, F.3
Whalley, D.4
-
66
-
-
0035501757
-
A comparison of static analysis and evolutionary testing for the verification of timing constraints
-
WEGENER, J. AND MUELLER, F. 2001. A comparison of static analysis and evolutionary testing for the verification of timing constraints. Real-Time Syst. 21, 3, 241-268.
-
(2001)
Real-time Syst
, vol.21
, Issue.3
, pp. 241-268
-
-
Wegener, J.1
Mueller, F.2
-
67
-
-
85029600625
-
Scheduling for reduced cpu energy
-
USENIX, Berkeley, CA
-
WEISER, M.,WELCH, B., DEMERS, A., AND SHENKER, S. 1994. Scheduling for reduced cpu energy. In Proceedings of the 1st Symposium on Operating Systems Design and Implementation. USENIX, Berkeley, CA.
-
(1994)
Proceedings of the 1st Symposium on Operating Systems Design and Implementation
-
-
Weiser, M.1
Welch, B.2
Demers, A.3
Shenker, S.4
-
68
-
-
0031369396
-
Timing analysis for datacaches and set-associative-caches
-
IEEE, Los Alamitos, CA
-
WHITE, R.,MUELLER, F., HEALY, C.,WHALLEY, D., AND HARMON, M. 1997. Timing analysis for datacaches and set-associative-caches. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA, 192-202.
-
(1997)
Proceedings of the Real-time Embedded Technology and Applications Symposium
, pp. 192-202
-
-
White, R.1
Mueller, F.2
Healy, C.3
Whalley, D.4
Harmon, M.5
-
69
-
-
0033327137
-
Timing analysis for data and wrap-around fill caches
-
WHITE, R. T., MUELLER, F., HEALY, C.,WHALLEY, D., AND HARMON, M. G. 1999. Timing analysis for data and wrap-around fill caches. Real-Time Syst. 17, 2/3, 209-233.
-
(1999)
Real-time Syst
, vol.17
, Issue.2-3
, pp. 209-233
-
-
White, R.T.1
Mueller, F.2
Healy, C.3
Whalley, D.4
Harmon, M.G.5
-
70
-
-
0036995554
-
Processor voltage scheduling for real-time tasks with nonpreemptable sections
-
IEEE, Los Alamitos, CA
-
ZHANG, F. AND CHANSON, S. T. 2002. Processor voltage scheduling for real-time tasks with nonpreemptable sections. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(2002)
Proceedings of the Real-time Systems Symposium
-
-
Zhang, F.1
Chanson, S.T.2
-
71
-
-
84879356072
-
Energy-aware modeling and scheduling of real-time tasks for dynamic voltage scaling
-
IEEE, Los Alamitos, CA
-
ZHONG, X. AND XU, C.-Z. 2005. Energy-aware modeling and scheduling of real-time tasks for dynamic voltage scaling. In Proceedings of the Real-Time Systems Symposium. IEEE, Los Alamitos, CA.
-
(2005)
Proceedings of the Real-time Systems Symposium
-
-
Zhong, X.1
U, C.-Z.X.2
-
72
-
-
7744227052
-
Feedback edf scheduling exploiting dynamic voltage scaling
-
IEEE, Los Alamitos, CA
-
ZHU, Y. AND MUELLER, F. 2004. Feedback edf scheduling exploiting dynamic voltage scaling. In Proceedings of the Real-Time Embedded Technology and Applications Symposium. IEEE, Los Alamitos, CA, 84-93.
-
(2004)
Proceedings of the Real-time Embedded Technology and Applications Symposium
, pp. 84-93
-
-
Zhu, Y.1
Mueller, F.2
-
73
-
-
31844452969
-
Feedback edf scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling
-
ACM, New York
-
ZHU, Y. AND MUELLER, F. 2005. Feedback edf scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling. In Proceedings of the Conference on Language, Compiler, and Tool Support for Embedded Systems. ACM, New York, 203-212.
-
(2005)
Proceedings of the Conference on Language, Compiler, and Tool Support for Embedded Systems
, pp. 203-212
-
-
Zhu, Y.1
Mueller, F.2
|