Leakage aware dynamic voltage scaling for real-time embedded systems

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 275-280

  Jejurikar, Ravindra ^a   Pereira, Cristiano ^b   Gupta, Rajesh ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Critical speed; EDF scheduling; Leakage power; Low power scheduling; Procrastication; Real time systems

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; ENERGY UTILIZATION; MATHEMATICAL MODELS; PROCESS CONTROL; SCHEDULING; THRESHOLD VOLTAGE;

CRITICAL SPEED; EDF SCHEDULING; LEAKAGE POWER; LOW POWER SCHEDULING; PROCRASTICATION;

REAL TIME SYSTEMS;

EID: 4444368993     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996650     Document Type: Conference Paper

References (28)

1. ITRS: 2002 edition http://public.itrs.net.
2. Berkeley Predictive Technology Models and BSIM4 http://www-device.eeecs.berkeley.edu/research.html.
3. H. Aydin, R. Melhem, D. Mossé, and P. M. Alvarez. Determining optimal processor speeds for periodic real-time tasks with different power characteristics. In Proceedings of EuroMicro Conference on Real-Time Systems, 2001.
4. H. Aydin, R. Melhem, D. Mossé, and P. M. Alvarez. Dynamic and aggressive scheduling techniques for power-aware real-time systems. In Proceedings of IEEE Real-Time Systems Symposium, December 2001.
5. S. Borkar. Design challenges of technology scaling. In IEEE Micro, pages 23-29, Aug 1999.
6. J. A. Butts and G. S. Sohi. A static power model for architects. In Intl. Symposium on Microarchitecture, 2000.
7. B. H. Calhoun, F. A. Honore, and A. Chandrakasan. Design methodology for fine-grained leakage control in mtcmos. In Proceedings of International Symposium on Low Power Electronics and Design, pages 104-109, 2003.
8. G. Carpenter. Low power soc for ibm's powerpc information appliance platform. In http://www.research.ibm.com/arl.
9. D. Duarte, N. Vijaykrishnan, M. J. Irwin, and Y.-F. Tsai. Impact of technology scaling and packaging on dynamic voltage scaling techniques. In 15th Annual IEEE International ASIC/SOC Conference, September 2002.
10. K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of International Symposium on Computer Architecture, June 2002.
11. Z. Hu, S. Kaxiras, and M. Martonosi. Let caches decay: Reducing leakage energy via exploitation of cache generational behavior. In ACM Transactions on Computer Systems, May 2002.
12. Intel PXA250/210 Processor. Intel Inc. (www.intel.com).
13. S. Irani, S. Shukla, and R. Gupta. Algorithms for power savings. In Proceedings of Symposium on Discrete Algorithms, Jan. 2003.
14. R. Jejurikar, C. Pereira, and R. Gupta. Leakage aware dynamic voltage scaling for real-time embedded systems. In CECS Technical Report #03-35, UC Irvine, Dec. 2003.
15. M. Johnson, D. Somasekhar, and K. Roy. Models and algorithms for bounds on leakage in cmos circuits. In IEEE Transactions on CAD, pages 714-725, 1999.
16. C. M. Krishna and Y. H. Lee. Voltage clock scaling adaptive scheduling techniques for low power in hard real-time systems. In Proceedings of Real-Time Technology and Applications Symposium, May 2000.
17. N. K. J. L. Yan, J. Luo. Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. In Proceedings of International Conferenceon Computer Aided Design, Nov. 2003.
18. H. G. Lee and N. Chang. Energy-aware memory allocation in heterogeneous non-volatile memory systems. In ISLPED, pages 420-423, 2003.
19. Y. Lee, K. P. Reddy, and C. M. Krishna. Scheduling techniques for reducing leakage power in hard real-time systems. In EcuroMicro Conf. on Real Time Systems, 2003.
20. J. W. S. Liu. Real-Time Systems. Prentice-Hall, 2000.
21. C. Locke, D. Vogel, and T. Mesler. Building a predictable avionics platform in ada: a case study. In Proceedings IEEE Real-Time Systems Symposium, 1991.
22. S. Martin, K. Flautner, T. Mudge, and D. Blaauw. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. In Proc. of Intl. Conference on Computer Aided Design, 2002.
23. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada. 1-v power supply highspeed digital circuit technology with multithreshold- voltage cmos. In IEEE Journal of Solid- State Circuits, pages 847-854, 1995.
24. C. Neau and K. Roy. Optimal body bias selection for leakage improvement and process compensation over different technology generations. In Proceedings of International Symposium on Low Power Electronics and Design, 2003.
25. J. Pouwelse, K. Langendoen, and H. Sips. Energy priority scheduling for variable voltage processors. In Proceedings of the 2001 International Symposium on Low Power Electronics and Design, pages 28-33, 2001.
26. G. Quan and X. Hu. Minimum energy fixed-priority scheduling for variable voltage processors. In Proceedings of Design Automation and Test in Europe, March 2002.
27. Y. Shin, K. Choi, and T. Sakurai. Power optimization of real-time embedded systems on variable speed processors. In Proceedings of International Conference on Computer Aided Design, pages 365-368, 2000.
28. Transmeta Crusoe Processor. Transmeta Inc. (http://www.transmeta.com/technology).