Supporting timing analysis by automatic bounding of loop iterations

Real-Time Systems

Volumn 18, Issue 2, 2000, Pages 129-156

  Healy, Christopher ^b   Sjödin, Mikael ^b   Rustagi, Viresh ^a   Whalley, David ^b  

^a Silicon Spice   (United States)

^b UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING; ITERATIVE METHODS; RESPONSE TIME (COMPUTER SYSTEMS);

HARD REAL TIME SYSTEMS; STATIC TIMING ANALYSIS;

REAL TIME SYSTEMS;

EID: 0343341629     PISSN: 09226443     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008189014032     Document Type: Article

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