-
1
-
-
0242612078
-
Energy management for real-time embedded applications with compiler support
-
June
-
N. AbouGhazaleh, B. Childers, D. Mosse, R. Melhem, and M. Craven. Energy management for real-time embedded applications with compiler support. In ACMSIGPLAN Conference on Language, Compiler, and Tool Support for Embedded Systems, June 2003.
-
(2003)
ACMSIGPLAN Conference on Language, Compiler, and Tool Support for Embedded Systems
-
-
Aboughazaleh, N.1
Childers, B.2
Mosse, D.3
Melhem, R.4
Craven, M.5
-
3
-
-
84884185725
-
Collaborative operating system and compiler power management for real-time applications
-
May
-
N. AbouGhazaleh, D. Mosse, B. Childers, R. Melhem, and M. Craven. Collaborative operating system and compiler power management for real-time applications. In IEEE Real-Time Embedded Technology and Applications Symposium, May 2003.
-
(2003)
IEEE Real-Time Embedded Technology and Applications Symposium
-
-
Aboughazaleh, N.1
Mosse, D.2
Childers, B.3
Melhem, R.4
Craven, M.5
-
4
-
-
0038345691
-
Virtual simple architecture (VISA): Exceeding the complexity limit in safe real-time systems
-
June
-
A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, and F. Mueller. Virtual simple architecture (VISA): Exceeding the complexity limit in safe real-time systems. In International Symposium on Computer Architecture, pages 250-261, June 2003.
-
(2003)
International Symposium on Computer Architecture
, pp. 250-261
-
-
Anantaraman, A.1
Seth, K.2
Patil, K.3
Rotenberg, E.4
Mueller, F.5
-
5
-
-
21644456004
-
Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (visa)
-
Dec.
-
A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, and F. Mueller. Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (visa). In IEEE Real-Time Systems Symposium, pages 114-125, Dec. 2004.
-
(2004)
IEEE Real-Time Systems Symposium
, pp. 114-125
-
-
Anantaraman, A.1
Seth, K.2
Patil, K.3
Rotenberg, E.4
Mueller, F.5
-
9
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
Vancouver, British Columbia, June, IEEE Computer Society and ACM SIGARCH
-
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83-94, Vancouver, British Columbia, June 2000. IEEE Computer Society and ACM SIGARCH.
-
(2000)
Proceedings of the 27th Annual International Symposium on Computer Architecture
, pp. 83-94
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
10
-
-
0003510233
-
-
Technical Report CS-TR-96-1308, University of Wisconsin-Madison, CS Dept., July
-
D. Burger, T. Austin, and S. Bennett. Evaluating future microprocessors: The simplescalar toolset. Technical Report CS-TR-96-1308, University of Wisconsin-Madison, CS Dept., July 1996.
-
(1996)
Evaluating Future Microprocessors: The Simplescalar Toolset
-
-
Burger, D.1
Austin, T.2
Bennett, S.3
-
11
-
-
84879379607
-
-
C-Lab. Wcet benchmarks. Available from
-
C-Lab. Wcet benchmarks. Available from http://www.clab. de/home/en/download.html.
-
-
-
-
12
-
-
0030244313
-
Combining static worst-case timing analysis and program proof
-
R. Chapman, A. Burns, and A. Wellings. Combining static worst-case timing analysis and program proof. Real-Time Systems, 11(2):145-171, 1996.
-
(1996)
Real-Time Systems
, vol.11
, Issue.2
, pp. 145-171
-
-
Chapman, R.1
Burns, A.2
Wellings, A.3
-
13
-
-
0033733125
-
Worst case execution time analysis for a processor with branch prediction
-
A. Colin and I. Puaut. Worst case execution time analysis for a processor with branch prediction. Real-Time Systems, 18(2/3):249-174, 2001.
-
(2001)
Real-Time Systems
, vol.18
, Issue.2-3
, pp. 249-174
-
-
Colin, A.1
Puaut, I.2
-
14
-
-
0035279683
-
Intra-task voltage scheduling for low-energy hard real-time applications
-
March
-
J. K. D. Shin and S. Lee. Intra-task voltage scheduling for low-energy hard real-time applications. In IEEE Design and Test of Computers, March 2001.
-
(2001)
IEEE Design and Test of Computers
-
-
Shin, J.K.D.1
Lee, S.2
-
15
-
-
0033334995
-
Efficient and precise cache behavior prediction for real-time systems
-
Nov.
-
C. Ferdinand and R. Wilhelm. Efficient and precise cache behavior prediction for real-time systems. Real-Time Systems, 17(2/3):131-181, Nov. 1999.
-
(1999)
Real-Time Systems
, vol.17
, Issue.2-3
, pp. 131-181
-
-
Ferdinand, C.1
Wilhelm, R.2
-
18
-
-
85018376784
-
Policies for dynamic clock scheduling
-
Oct
-
D. Grunwald, P. Levis, C. M. III, M. Neufeld, and K. Farkas. Policies for dynamic clock scheduling. In Symp. on Operating Systems Design and Implementation, Oct 2000.
-
(2000)
Symp. on Operating Systems Design and Implementation
-
-
Grunwald, D.1
Levis, P.2
Iii, C.M.3
Neufeld, M.4
Farkas, K.5
-
20
-
-
0032713797
-
Bounding pipeline and instruction cache performance
-
Jan.
-
C. A. Healy, R. D. Arnold, F. Mueller, D. Whalley, and M. G. Harmon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, 48(1):53-70, Jan. 1999.
-
(1999)
IEEE Transactions on Computers
, vol.48
, Issue.1
, pp. 53-70
-
-
Healy, C.A.1
Arnold, R.D.2
Mueller, F.3
Whalley, D.4
Harmon, M.G.5
-
21
-
-
0029517739
-
Integrating the timing analysis of pipelining and instruction caching
-
Dec.
-
C. A. Healy, D. B. Whalley, and M. G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In IEEE Real-Time Systems Symposium, pages 288-297, Dec. 1995.
-
(1995)
IEEE Real-Time Systems Symposium
, pp. 288-297
-
-
Healy, C.A.1
Whalley, D.B.2
Harmon, M.G.3
-
22
-
-
0036997038
-
A fast resource synthesis technique for energy-efficient real-time systems
-
Dec.
-
D. Kang, S. Crago, and J. Suh. A fast resource synthesis technique for energy-efficient real-time systems. In IEEE Real-Time Systems Symposium, Dec. 2002.
-
(2002)
IEEE Real-Time Systems Symposium
-
-
Kang, D.1
Crago, S.2
Suh, J.3
-
23
-
-
0038682021
-
Voltage-clock scaling for low energy consumption in fixed-priority real-time systems
-
Y.-H. Lee and C. M. Krishna. Voltage-clock scaling for low energy consumption in fixed-priority real-time systems. Real-Time Syst., 24(3):303-317, 2003.
-
(2003)
Real-Time Syst.
, vol.24
, Issue.3
, pp. 303-317
-
-
Lee, Y.-H.1
Krishna, C.M.2
-
24
-
-
0030414718
-
Cache modeling for realtime software: Beyond direct mapped instruction caches
-
Dec.
-
Y.-T. S. Li, S. Malik, and A.Wolfe. Cache modeling for realtime software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254-263, Dec. 1996.
-
(1996)
IEEE Real-Time Systems Symposium
, pp. 254-263
-
-
Li, Y.-T.S.1
Malik, S.2
Wolfe, A.3
-
25
-
-
0003039244
-
An accurate worst case timing analysis for RISC processors
-
Dec.
-
S.-S. Lim, Y. H. Bae, G. T. Jang, B.-D. Rhee, S. L. Min, C. Y. Park, H. Shin, and C. S. Kim. An accurate worst case timing analysis for RISC processors. In IEEE Real-Time Systems Symposium, pages 97-108, Dec. 1994.
-
(1994)
IEEE Real-Time Systems Symposium
, pp. 97-108
-
-
Lim, S.-S.1
Bae, Y.H.2
Jang, G.T.3
Rhee, B.-D.4
Min, S.L.5
Park, C.Y.6
Shin, H.7
Kim, C.S.8
-
26
-
-
84974687699
-
Scheduling algorithms for multiprogramming in a hard-real-time environment
-
Jan.
-
C. Liu and J. Layland. Scheduling algorithms for multiprogramming in a hard-real-time environment. J. of the Association for Computing Machinery, 20(1):46-61, Jan. 1973.
-
(1973)
J. of the Association for Computing Machinery
, vol.20
, Issue.1
, pp. 46-61
-
-
Liu, C.1
Layland, J.2
-
28
-
-
84879371629
-
Using object oriented methods in Ada 95 to implement linda
-
K. Lundqvist and G.Wall. Using object oriented methods in Ada 95 to implement linda. In Ada Europe, 1996.
-
(1996)
Ada Europe
-
-
Lundqvist, K.1
Wall, G.2
-
30
-
-
24944536861
-
Timing analysis for sensor network nodes of the atmega processor family
-
Mar.
-
S. Mohan, F. Mueller, D. Whalley, and C. Healy. Timing analysis for sensor network nodes of the atmega processor family. In IEEE Real-Time Embedded Technology and Applications Symposium, pages 405-414, Mar. 2005.
-
(2005)
IEEE Real-Time Embedded Technology and Applications Symposium
, pp. 405-414
-
-
Mohan, S.1
Mueller, F.2
Whalley, D.3
Healy, C.4
-
32
-
-
0033732401
-
Timing analysis for instruction caches
-
May
-
F. Mueller. Timing analysis for instruction caches. Real-Time Systems, 18(2/3):209-239, May 2000.
-
(2000)
Real-Time Systems
, vol.18
, Issue.2-3
, pp. 209-239
-
-
Mueller, F.1
-
33
-
-
0027556297
-
Predicting program execution times by analyzing static and dynamic program paths
-
Mar.
-
C. Y. Park. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems, 5(1):31-61, Mar. 1993.
-
(1993)
Real-Time Systems
, vol.5
, Issue.1
, pp. 31-61
-
-
Park, C.Y.1
-
35
-
-
5644277636
-
Real-time dynamic voltage scaling for low-power embedded operating systems
-
P. Pillai and K. Shin. Real-time dynamic voltage scaling for low-power embedded operating systems. In Symposium on Operating Systems Principles, 2001.
-
(2001)
Symposium on Operating Systems Principles
-
-
Pillai, P.1
Shin, K.2
-
36
-
-
0000039023
-
Calculating the maximum execution time of real-time programs
-
Sept.
-
P. Puschner and C. Koza. Calculating the maximum execution time of real-time programs. Real-Time Systems, 1(2):159-176, Sept. 1989.
-
(1989)
Real-Time Systems
, vol.1
, Issue.2
, pp. 159-176
-
-
Puschner, P.1
Koza, C.2
-
38
-
-
0348195821
-
Fast: Frequency-aware static timing analysis
-
Dec.
-
K. Seth, A. Anantaraman, F. Mueller, and E. Rotenberg. Fast: Frequency-aware static timing analysis. In IEEE Real-Time Systems Symposium, pages 40-51, Dec. 2003.
-
(2003)
IEEE Real-Time Systems Symposium
, pp. 40-51
-
-
Seth, K.1
Anantaraman, A.2
Mueller, F.3
Rotenberg, E.4
-
40
-
-
1542330092
-
An abstract interpretation-based timing validation of hard real-time avionics
-
June
-
S. Thesing, J. Souyris, R. Heckmann, F. R. andM. Langenbach, R. Wilhelm, and C. Ferdinand. An Abstract Interpretation-Based Timing Validation of Hard Real-Time Avionics. In Proceedings of the International Performance and Dependability Symposium (IPDS), June 2003.
-
(2003)
Proceedings of the International Performance and Dependability Symposium (IPDS)
-
-
Thesing, S.1
Souyris, J.2
Heckmann, R.3
Langenbach, F.R.4
Wilhelm, R.5
Ferdinand, C.6
-
42
-
-
17244380810
-
Parametric timing analysis
-
Aug.
-
E. Vivancos, C. Healy, F. Mueller, and D.Whalley. Parametric timing analysis. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Embedded Systems, volume 36 of ACM SIGPLAN Notices, pages 88-93, Aug. 2001.
-
(2001)
ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Embedded Systems, Volume 36 of ACM SIGPLAN Notices
, pp. 88-93
-
-
Vivancos, E.1
Healy, C.2
Mueller, F.3
Whalley, D.4
-
43
-
-
0035501757
-
A comparison of static analysis and evolutionary testing for the verification of timing constraints
-
Nov.
-
J. Wegener and F. Mueller. A comparison of static analysis and evolutionary testing for the verification of timing constraints. Real-Time Systems, 21(3):241-268, Nov. 2001.
-
(2001)
Real-Time Systems
, vol.21
, Issue.3
, pp. 241-268
-
-
Wegener, J.1
Mueller, F.2
-
45
-
-
0033327137
-
Timing analysis for data and wrap-around fill caches
-
Nov.
-
R. T. White, F. Mueller, C. Healy, D. Whalley, and M. G. Harmon. Timing analysis for data and wrap-around fill caches. Real-Time Systems, 17(2/3):209-233, Nov. 1999.
-
(1999)
Real-Time Systems
, vol.17
, Issue.2-3
, pp. 209-233
-
-
White, R.T.1
Mueller, F.2
Healy, C.3
Whalley, D.4
Harmon, M.G.5
-
46
-
-
0036995554
-
Processor voltage scheduling for real-time tasks with non-preemptable sections
-
Dec.
-
F. Zhang and S. T. Chanson. Processor voltage scheduling for real-time tasks with non-preemptable sections. In IEEE Real-Time Systems Symposium, Dec. 2002.
-
(2002)
IEEE Real-Time Systems Symposium
-
-
Zhang, F.1
Chanson, S.T.2
|