-
2
-
-
0000181650
-
-
chapter An appropriate engineering approach, Prentice-Hall International, Inc.
-
A. Burns. Preemptive priority based scheduling, chapter An appropriate engineering approach, pages 225-248. Prentice-Hall International, Inc., 1994.
-
(1994)
Preemptive Priority Based Scheduling
, pp. 225-248
-
-
Burns, A.1
-
3
-
-
0040354316
-
Techniques to increase the schedulable utilization of cache-based preemptive real-time systems
-
J. V. Busquets-Mataix, D. Gil, P. Gil, and A. Wellings. Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. Journal of System Architecture, 46:357-378, 2000.
-
(2000)
Journal of System Architecture
, vol.46
, pp. 357-378
-
-
Busquets-Mataix, J.V.1
Gil, D.2
Gil, P.3
Wellings, A.4
-
5
-
-
0035007992
-
Satisfying timing constraints of preemptive real-time tasks through task layout technique
-
January
-
A. Datta, S. Choudhury, A. Basu, H. Tomiyama, and N. Dutt. Satisfying timing constraints of preemptive real-time tasks through task layout technique. In IEEE VLSI Design, pages 97-102, January 2001.
-
(2001)
IEEE VLSI Design
, pp. 97-102
-
-
Datta, A.1
Choudhury, S.2
Basu, A.3
Tomiyama, H.4
Dutt, N.5
-
6
-
-
0029345326
-
An accurate worst case timing analysis for rise processors
-
July
-
S.-S. L. et al. An accurate worst case timing analysis for rise processors. IEEE Transactions on Software Engineering, 21(7):593-603, July 1995.
-
(1995)
IEEE Transactions on Software Engineering
, vol.21
, Issue.7
, pp. 593-603
-
-
L., S.-S.1
-
7
-
-
27644492319
-
-
Infineon. Tricore 1 manual http://www.infineon.com.
-
Tricore 1 Manual
-
-
-
9
-
-
0024933416
-
Smart (strategic memory allocation for real-time) cache design
-
D. B. Kirk. Smart (strategic memory allocation for real-time) cache design. In IEEE Real-Time Systems Symposium, pages 229-239, 1989.
-
(1989)
IEEE Real-time Systems Symposium
, pp. 229-239
-
-
Kirk, D.B.1
-
10
-
-
0035441708
-
Bounding cache-related preemption delay for real-time systems
-
November
-
C.-G. Lee, K. Lee, and J. H. et al. Bounding cache-related preemption delay for real-time systems. IEEE Transactions on software engineering, 27(9): 805-826, November 2001.
-
(2001)
IEEE Transactions on Software Engineering
, vol.27
, Issue.9
, pp. 805-826
-
-
Lee, C.-G.1
Lee, K.2
H., J.3
-
11
-
-
31844453825
-
Os-controlled cache predictability for real-time systems
-
Montreal, Canada, June 9-11
-
J. Liedtke, H. Härtig, and M. Hohmuth. Os-controlled cache predictability for real-time systems. In RTAS, Montreal, Canada, June 9-11 1997.
-
(1997)
RTAS
-
-
Liedtke, J.1
Härtig, H.2
Hohmuth, M.3
-
12
-
-
27644461266
-
Accurate estimation of cache-related preemption delay
-
Newport Beach, CA, USA, Oct.
-
H. S. Negi, T. Mitra, and A. Roychoudhury. Accurate estimation of cache-related preemption delay. In CODES+ISSS'03, Newport Beach, CA, USA, Oct. 2003.
-
(2003)
CODES+ISSS'03
-
-
Negi, H.S.1
Mitra, T.2
Roychoudhury, A.3
-
13
-
-
0003631973
-
-
Kluwer Academic Publishers,Norwell, MA
-
P. R. Panda, N. D. Dutt, and A. Nicolau. Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration. Kluwer Academic Publishers,Norwell, MA, 1999.
-
(1999)
Memory Issues in Embedded Systems-on-chip: Optimizations and Exploration
-
-
Panda, P.R.1
Dutt, N.D.2
Nicolau, A.3
-
14
-
-
27644451676
-
Scheduling analysis with respect to hardware related preemption delay
-
London, UK, Dec.
-
S. M. Petters and G. Färber. Scheduling analysis with respect to hardware related preemption delay. In Workshop on Real-Time Embedded Systems, London, UK, Dec. 2001.
-
(2001)
Workshop on Real-time Embedded Systems
-
-
Petters, S.M.1
Färber, G.2
-
15
-
-
0036991624
-
Low-complexity algorihtms for static cache locking in multitasking hard real-time systems
-
I. Puaut and D. Decotigny. Low-complexity algorihtms for static cache locking in multitasking hard real-time systems. In RTSS, 2002.
-
(2002)
RTSS
-
-
Puaut, I.1
Decotigny, D.2
-
16
-
-
27644442533
-
Multiple process execution in cache related preemption delay analysis
-
Pisa, Italy, Sept.
-
J. Staschulat and R. Ernst. Multiple process execution in cache related preemption delay analysis. In EMSOFT, Pisa, Italy, Sept. 2004.
-
(2004)
EMSOFT
-
-
Staschulat, J.1
Ernst, R.2
|