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Volumn 17, Issue 2, 1999, Pages 209-233

Timing analysis for data and wrap-around fill caches

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DATA FLOW ANALYSIS; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

EID: 0033327137     PISSN: 09226443     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008190423977     Document Type: Article
Times cited : (37)

References (30)
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    • (1991) Microprocessors and Microsystems , vol.15 , Issue.9 , pp. 459-472
    • Davidson, J.W.1    Whalley, D.B.2
  • 11
    • 0029517739 scopus 로고
    • Integrating the timing analysis of pipelining and instruction caching
    • Healy, C. A., Whalley, D. B., and Harmon, M. G. 1995. Integrating the timing analysis of pipelining and instruction caching. IEEE Real-Time Systems Symposium, pp. 288-297.
    • (1995) IEEE Real-Time Systems Symposium , pp. 288-297
    • Healy, C.A.1    Whalley, D.B.2    Harmon, M.G.3
  • 15
    • 0029546911 scopus 로고
    • Efficient microarchitecture modeling and path analysis for real-time software
    • Li, Y.-T. S., Malik, S., and Wolfe, A. 1995. Efficient microarchitecture modeling and path analysis for real-time software. IEEE Real-Time Systems Symposium, pp. 298-397.
    • (1995) IEEE Real-Time Systems Symposium , pp. 298-397
    • Li, Y.-T.S.1    Malik, S.2    Wolfe, A.3
  • 16
    • 0030414718 scopus 로고    scopus 로고
    • Cache modeling for real-time software: Beyond direct mapped instruction caches
    • Li, Y.-T. S., Malik, S., and Wolfe, A. 1996. Cache modeling for real-time software: Beyond direct mapped instruction caches. IEEE Real-Time Systems Symposium, pp. 254-263.
    • (1996) IEEE Real-Time Systems Symposium , pp. 254-263
    • Li, Y.-T.S.1    Malik, S.2    Wolfe, A.3
  • 18
    • 84974687699 scopus 로고
    • Scheduling algorithms for multiprogramming in a hard-real-time environment
    • Liu, C. L., and Layland, J. W. 1973. Scheduling algorithms for multiprogramming in a hard-real-time environment. Journal of the Association for Computing Machinery 20(1): 46-61.
    • (1973) Journal of the Association for Computing Machinery , vol.20 , Issue.1 , pp. 46-61
    • Liu, C.L.1    Layland, J.W.2
  • 20
    • 0027556297 scopus 로고
    • Predicting program execution times by analyzing static and dynamic program paths
    • Park, C. Y. 1993. Predicting program execution times by analyzing static and dynamic program paths. Real-Time Systems 5(1): 31-61.
    • (1993) Real-Time Systems , vol.5 , Issue.1 , pp. 31-61
    • Park, C.Y.1
  • 23
    • 0000039023 scopus 로고
    • Calculating the maximum execution time of real-time programs
    • Puschner, P., and Koza, C. 1989. Calculating the maximum execution time of real-time programs. Real-Time Systems 1(2): 159-176.
    • (1989) Real-Time Systems , vol.1 , Issue.2 , pp. 159-176
    • Puschner, P.1    Koza, C.2
  • 26
  • 30
    • 0027684495 scopus 로고
    • Pipelined processors and worst case execution times
    • Zhang, N., Burns, A., and Nicholson, M. 1993. Pipelined processors and worst case execution times. Real-Time Systems 5(4): 319-343.
    • (1993) Real-Time Systems , vol.5 , Issue.4 , pp. 319-343
    • Zhang, N.1    Burns, A.2    Nicholson, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.