Verilog HDL, powered by PLI: A suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 330-333

  Saifhashemi, Arash ^a   Pedram, Hossein ^a  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Asynchronous circuits; Channel; CHP; CSP; PLI; Verilog

Indexed keywords

ABSTRACTING; ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER PROGRAMMING LANGUAGES; DATA COMMUNICATION SYSTEMS; MACROS; NETWORK PROTOCOLS;

COMMUNICATIONG SEQUENTIAL PROCESSES (CSP);

LOGIC DESIGN;

EID: 0041633864     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Alain J. Martin. Synthesis of Asynchronous VLSI Circuits. Internal Report. Caltech-CS-TR-93-28. California Institute of Technology, Pasadena, CA. 1993
2. C.A.R. Hoare. Communicating Sequential Processes. CACM 21, 8, pp 666-677, 1978
3. Chris J. Myers. Asynchronous Circuit Design. John Wiley & Sons, INC.
4. Jens Sparsoe and Steve Furber. Principles of Asynchronous Circuit Design. Kluwer Academic Publishers.
5. Philip Endecott and S. Furber. Modelling and Simulation of Asynchronous Systems using the LARD. http://www.cs.man.ac.uk/amulet/projects/lard