A bottom-up approach to on-chip signal integrity

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2799, Issue , 2003, Pages 540-549

  Acquaviva, Andrea ^a   Bogliolo, Alessandro ^a  

^a UNIVERSITY OF URBINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BUSBARS; DIGITAL INTEGRATED CIRCUITS;

ARBITRARY NOISE; BOTTOM UP APPROACH; FITTING MODEL; NEW APPROACHES; ON-CHIP COMMUNICATION CHANNELS; ON-CHIP SIGNALS; SIGNAL INTEGRITY; TRANSMISSION ERROR;

BIT ERROR RATE;

EID: 33750918453     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39762-5_60     Document Type: Article

References (5)

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3. Hall, S.H., Hall, G.W., McCall, J.A.: High-Speed Digital System Design, A Handbook of Interconnect Theory and Design Practices. John Wiley & Sons (2000)
4. Bogliolo, A., Olivo, P.: Dealing with noise margins in high-speed voltage-mode signaling. In Proc. of IEEE Workshop on Signal Propagation on Interconnects (2002).
5. Bogliolo, A.: Encodings for High-Performance Energy-Efficient Signaling. In Proc. of IEEE/ACM Int.l Symposium on Low-Power Electronics and Design (2001).