Highly fault-tolerant FPGA processor by degrading strategy

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC

Volumn 2002-January, Issue , 2002, Pages 75-78

  Nakamura, Yousuke ^a   Hiraki, Kei ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

Central Processing Unit; Circuit faults; Computer architecture; Degradation; Electrical fault detection; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Information science; Logic

Indexed keywords

COMPUTATION THEORY; COMPUTER ARCHITECTURE; DEGRADATION; ELECTRIC FAULT LOCATION; FAULT DETECTION; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION SCIENCE; LOGIC CIRCUITS; PROGRAM PROCESSORS;

CIRCUIT FAULTS; CONFIGURABLE LOGIC BLOCKS; ELECTRICAL FAULT DETECTIONS; FAULT TOLERANT SYSTEMS; FPGA ARCHITECTURES; LOGIC; REDUNDANT CIRCUITS; SUBSTITUTION METHOD;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 35649016252     PISSN: 15410110     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PRDC.2002.1185621     Document Type: Conference Paper

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