-
1
-
-
27344448860
-
Analysis of Error Recovery Schemes for Networks on Chips
-
S. Murali, T. Theocharides, N. Vijaykrishnan, M.J. Irwin, L. Benini, and G.D. Micheli, "Analysis of Error Recovery Schemes for Networks on Chips", IEEE Design & Test of Computers, Volume 22, Issue 5, 2005, pp. 434-442 .
-
(2005)
IEEE Design & Test of Computers
, vol.22
, Issue.5
, pp. 434-442
-
-
Murali, S.1
Theocharides, T.2
Vijaykrishnan, N.3
Irwin, M.J.4
Benini, L.5
Micheli, G.D.6
-
2
-
-
46749140919
-
Essential Fault-Tolerance Metrics for NoC Infrastructures
-
C. Grecu, L. Anghel, P.P. Pande, A. Ivanov, and R. Saleh, "Essential Fault-Tolerance Metrics for NoC Infrastructures", 13th IOLTS, 2007, pp. 37-42.
-
(2007)
13th IOLTS
, pp. 37-42
-
-
Grecu, C.1
Anghel, L.2
Pande, P.P.3
Ivanov, A.4
Saleh, R.5
-
3
-
-
33847230905
-
A Dynamic Routing Mechanism for Network on Chips
-
M. Ali, M. Welzl, and S. Hellebrand, "A Dynamic Routing Mechanism for Network on Chips", Norchip Conference, 2005, pp. 70-73.
-
(2005)
Norchip Conference
, pp. 70-73
-
-
Ali, M.1
Welzl, M.2
Hellebrand, S.3
-
4
-
-
84906699571
-
An Efficient Fault-Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
-
M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, "An Efficient Fault-Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip", International Journal of high Performance System Architecture, Vol.1, No.2, 2007, pp. 113-123.
-
(2007)
International Journal of high Performance System Architecture
, vol.1
, Issue.2
, pp. 113-123
-
-
Ali, M.1
Welzl, M.2
Hessler, S.3
Hellebrand, S.4
-
5
-
-
44149126468
-
A Lightweight Fault-Tolerant Mechanism for Networks-on-Chip
-
M. Koibuchi, H. Matsutani, H. Amano, and T.M. Pinkston, "A Lightweight Fault-Tolerant Mechanism for Networks-on-Chip", Second ACM/IEEE International Symposium Networks-on-Chip, 2008, pp.13-22.
-
(2008)
Second ACM/IEEE International Symposium Networks-on-Chip
, pp. 13-22
-
-
Koibuchi, M.1
Matsutani, H.2
Amano, H.3
Pinkston, T.M.4
-
6
-
-
44149107193
-
Crosstalk and SEU Aware Networks on Chips
-
A.P. Frantz, M. Cassel, F.L. Kastensmidt, E. Cota, and L. Carro, "Crosstalk and SEU Aware Networks on Chips", IEEE Design and Test of Computers, 2007, pp.340-350.
-
(2007)
IEEE Design and Test of Computers
, pp. 340-350
-
-
Frantz, A.P.1
Cassel, M.2
Kastensmidt, F.L.3
Cota, E.4
Carro, L.5
-
7
-
-
39749110032
-
Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk
-
A.P. Frantz, F.L. Kastensmidt, L. Carro, and E. Cota, "Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk", IEEE International test Conference, 2006, pp. 1-9.
-
(2006)
IEEE International test Conference
, pp. 1-9
-
-
Frantz, A.P.1
Kastensmidt, F.L.2
Carro, L.3
Cota, E.4
-
8
-
-
46749088674
-
An Analytical Model for Reliability Evaluation of NoC Architectures
-
A. Dalirsani, M. Hosseinabady, and Z. Navabi, "An Analytical Model for Reliability Evaluation of NoC Architectures", 13th IOLTS, 2007, pp. 49-56.
-
(2007)
13th IOLTS
, pp. 49-56
-
-
Dalirsani, A.1
Hosseinabady, M.2
Navabi, Z.3
-
9
-
-
84964966055
-
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models
-
H.R. Zarandi, S.G. Miremadi, and A. Ejlali, "Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models", Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 485-492.
-
(2003)
Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems
, pp. 485-492
-
-
Zarandi, H.R.1
Miremadi, S.G.2
Ejlali, A.3
-
10
-
-
8444238226
-
Soft Errors in Commercial Integrated Circuits
-
R. C. Baumann, "Soft Errors in Commercial Integrated Circuits", International Journal of High Speed Electronics and Systems, Vol. 14, No. 2, 2004, pp. 299-309.
-
(2004)
International Journal of High Speed Electronics and Systems
, vol.14
, Issue.2
, pp. 299-309
-
-
Baumann, R.C.1
|