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Volumn , Issue , 2010, Pages 540-545

Investigation of transient fault effects in an asynchronous NoC router

Author keywords

Asynchronous; Component; Fault tolerance; NoC

Indexed keywords

ASYNCHRONOUS COMPONENTS; ASYNCHRONOUS DESIGN; ASYNCHRONOUS ROUTERS; FAILURE RATE; FAULT INJECTION; FAULT INJECTOR; FAULT MODEL; FAULT-TOLERANT; HANDSHAKING; SIMULATION-BASED; TRANSIENT AND PERMANENT FAULT; TRANSIENT FAULTS; VERILOG;

EID: 77952665785     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PDP.2010.21     Document Type: Conference Paper
Times cited : (12)

References (17)
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    • Integrated Circuit and System Design Power and Timing Modeling, Optimization and Simulation
    • A. Acquaviva, and A. Bogliolo, "A Bottom-up Approach to On-Chip Signal Integrity", Lecture Notes in Computer Science, Volume 2799, 2003, pp. 540-549. (Pubitemid 37171589)
    • (2003) LECTURE NOTES in COMPUTER SCIENCE , Issue.2799 , pp. 540-549
    • Acquaviva, A.1    Bogliolo, A.2
  • 5
    • 0031078886 scopus 로고    scopus 로고
    • EMI Effects and Timing Design for Increased Reliability in Digital Systems
    • J.F. Chappel, and S.G. Zaky, "EMI Effects and Timing Design for Increased Reliability in Digital Systems," IEEE Transactions on Circuits and System, 1997, pp. 130-142.
    • (1997) IEEE Transactions on Circuits and System , pp. 130-142
    • Chappel, J.F.1    Zaky, S.G.2
  • 7
    • 84906699571 scopus 로고    scopus 로고
    • An Efficient Fault-Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
    • M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, "An Efficient Fault-Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip", International Journal of high Performance System Architecture, Vol.1, No.2, 2007, pp. 113-123.
    • (2007) International Journal of High Performance System Architecture , vol.1 , Issue.2 , pp. 113-123
    • Ali, M.1    Welzl, M.2    Hessler, S.3    Hellebrand, S.4
  • 8
    • 34249746758 scopus 로고    scopus 로고
    • Degradable Mesh-based on-Chip Networks Using Programmable Routing Tables
    • A. Shahabi, M. Honarmand, H. Sohofi, and Z. Navabi, "Degradable Mesh-based on-Chip Networks Using Programmable Routing Tables", IEICE Electron. Express, Vol.4, No. 10, 2007, pp. 332-339.
    • (2007) IEICE Electron. Express , vol.4 , Issue.10 , pp. 332-339
    • Shahabi, A.1    Honarmand, M.2    Sohofi, H.3    Navabi, Z.4
  • 14
    • 0041633864 scopus 로고    scopus 로고
    • Verilog HDL, Powered by PLI: A Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction
    • A. Seifhashemi, H. Pedram, "Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction", Proceedings of 40th DAC, 2003, pp. 330-333.
    • Proceedings of 40th DAC, 2003 , pp. 330-333
    • Seifhashemi, A.1    Pedram, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.