An investigation of fault tolerance behavior of 32-bit DLX processor

Proceedings - 2009 2nd International Conference on Dependability, DEPEND 2009

Volumn , Issue , 2009, Pages 93-98

  Yaghini, Pooria M ^a   Zarandi, Hamid R ^a   Eghbal, Ashkan ^a   Jafarzadeh, Akbar ^b   Eskandari, Saeedeh ^b  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

^b ISLAMIC AZAD UNIVERSITY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLES; FAILURE RATE; FAULT LATENCY; SIMULATION-BASED METHOD; SYSTEM FAILURES; VHDL-MODEL;

ERRORS; FAULT TOLERANCE; FAULT TREE ANALYSIS; SIMULATORS; SYSTEMS ENGINEERING;

QUALITY ASSURANCE;

EID: 70449449217     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DEPEND.2009.20     Document Type: Conference Paper

References (18)

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