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1
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0036149420
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Networks on Chips: A New SoC Paradigm
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Jan
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L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, Jan. 2002, pp. 70-78.
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(2002)
IEEE Computer
, pp. 70-78
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Benini, L.1
De Micheli, G.2
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2
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27344437058
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Design, Synthesis and Test of Networks on Chip
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P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli, "Design, Synthesis and Test of Networks on Chip", IEEE Design and Test of Computers, Vol. 22, No. 5, 2005, pp. 404-413.
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(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.5
, pp. 404-413
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Pande, P.1
Grecu, C.2
Ivanov, A.3
Saleh, R.4
De Micheli, G.5
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3
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3042669096
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QNoC: QoS architecture and design process for Network on Chip
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Dec
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E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "QNoC: QoS architecture and design process for Network on Chip", Special issue on Networks on Chip, The Journal of Systems Architecture, Dec. 2003
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(2003)
Special issue on Networks on Chip, The Journal of Systems Architecture
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Bolotin, E.1
Cidon, I.2
Ginosar, R.3
Kolodny, A.4
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4
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3042660381
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An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming
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A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, P. Wielage, " An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming", Proceedings of the IEEE Design, Automation and Test in Europe (DATE), 2004, Vol: 2, pp: 878- 883.
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(2004)
Proceedings of the IEEE Design, Automation and Test in Europe (DATE)
, vol.2
, pp. 878-883
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Radulescu, A.1
Dielissen, J.2
Goossens, K.3
Rijpkema, E.4
Wielage, P.5
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5
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20444467586
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Error Control Schemes for On-Chip Communication Links: The Energy-Reliability Tradeoff
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June
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D. Bertozzi, L. Benini, G. De Micheli, "Error Control Schemes for On-Chip Communication Links: The Energy-Reliability Tradeoff", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, June 2005, pp. 818-831.
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(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.6
, pp. 818-831
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Bertozzi, D.1
Benini, L.2
De Micheli, G.3
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6
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23744468720
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Coding for System-on-Chip Networks: A Unified Framework
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June
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S. R. Sridhara, and N. R. Shanbhag, "Coding for System-on-Chip Networks: A Unified Framework", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 13, No. 6, June 2005, pp. 655-667.
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(2005)
IEEE Transactions on Very Large Scale Integration (TVLSI) Systems
, vol.13
, Issue.6
, pp. 655-667
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Sridhara, S.R.1
Shanbhag, N.R.2
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7
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0035704588
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Bus guardians: An effective solution for online detection and correction of faults affecting system-on-chip buses
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Dec
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M. Lajolo, "Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses", IEEE Transactions on VLSI Systems, Vol. 9, Issue: 6, Dec. 2001, pp: 974-982.
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(2001)
IEEE Transactions on VLSI Systems
, vol.9
, Issue.6
, pp. 974-982
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Lajolo, M.1
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8
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84893755546
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Low power error resilient encoding for on-chip data buses
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March
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D. Bertozzi, L. Benini, G. De Micheli, "Low power error resilient encoding for on-chip data buses", Proceedings of the Design, Automation and Test in Europe Conference (DATE), 4-8 March 2002, pp: 102-109.
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(2002)
Proceedings of the Design, Automation and Test in Europe Conference (DATE), 4-8
, pp. 102-109
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Bertozzi, D.1
Benini, L.2
De Micheli, G.3
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11
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4544376708
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Fault Tolerant Algorithms for Network-On-Chip Interconnect
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M. Pirretti, G. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, "Fault Tolerant Algorithms for Network-On-Chip Interconnect", Proceedings of IEEE ISVLSI 2004, pp: 46-51.
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(2004)
Proceedings of IEEE ISVLSI
, pp. 46-51
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Pirretti, M.1
Link, G.2
Brooks, R.R.3
Vijaykrishnan, N.4
Kandemir, M.5
Irwin, M.J.6
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12
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38749126805
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Design of low power and reliable networks on chip through joint crosstalk avoidance and forward error correction coding
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P. P. Pande, A. Ganguly, B. Feero, B. Belzer, C. Grecu, "Design of low power and reliable networks on chip through joint crosstalk avoidance and forward error correction coding", Proceedings of IEEE DFT Symposium, DFT'06, 2006, pp:466-476.
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(2006)
Proceedings of IEEE DFT Symposium, DFT'06
, pp. 466-476
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Pande, P.P.1
Ganguly, A.2
Feero, B.3
Belzer, B.4
Grecu, C.5
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13
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27344448860
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Analysis of error recovery schemes for networks on chips
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Sept.-Oct
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S. Murali, T. Theocharides,. N. Vijaykrishnan, M. J. Irwin, L. Benini, G. De Micheli, "Analysis of error recovery schemes for networks on chips", IEEE Design and Test of Computers, Sept.-Oct. 2005, Vol: 22, Issue: 5, pp: 434- 442.
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(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.5
, pp. 434-442
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Murali, S.1
Theocharides, T.2
Vijaykrishnan, N.3
Irwin, M.J.4
Benini, L.5
De Micheli, G.6
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14
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34247281589
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On-line fault detection and location for NoC interconnects
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C. Grecu, A. Ivanov, R. Saleh, E. S. Sogomonyan, P. P. Pande, "On-line fault detection and location for NoC interconnects," Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, pp. 145-150.
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(2006)
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS'06)
, pp. 145-150
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Grecu, C.1
Ivanov, A.2
Saleh, R.3
Sogomonyan, E.S.4
Pande, P.P.5
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16
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0042111484
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A. Jantsch and H. Tenhunen, editors, Kluwer Academic Publishers
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A. Jantsch and H. Tenhunen, editors, Networks on Chip, Kluwer Academic Publishers, 2003.
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(2003)
Networks on Chip
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17
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84867921709
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Connectivity and fault-tolerance of hyperdigraphs
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D. Ferrero, C. Padró, "Connectivity and fault-tolerance of hyperdigraphs", Discrete Applied Mathematics 117 (2002), pp: 15-26.
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(2002)
Discrete Applied Mathematics
, vol.117
, pp. 15-26
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Ferrero, D.1
Padró, C.2
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18
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27944452666
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S Manolache, P Eles, Z Peng, Fault and Energy-Aware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC, Proceedings of Design Automation Conference, DAC 2005, pp: 266 - 269.
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S Manolache, P Eles, Z Peng, "Fault and Energy-Aware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC", Proceedings of Design Automation Conference, DAC 2005, pp: 266 - 269.
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