Offset voltage estimation model for latch-type sense amplifiers

IET Circuits, Devices and Systems

Volumn 4, Issue 6, 2010, Pages 503-513

  Woo, S H ^a   Kang, H ^a   Park, K ^b   Jung, S O ^a  

^a Yonsei University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMMONLY USED; DRAIN-INDUCED BARRIER LOWERING; ESTIMATION MODELS; LARGE-SIGNALS; MONTE CARLO; OFFSET VOLTAGE; SENSE AMPLIFIER; SMALL SIGNAL; STACK EFFECT; STANDARD DEVIATION; STATISTICAL DISTRIBUTION; TECHNOLOGY SCALING; VARIANCE MODELS;

ESTIMATION; STATIC RANDOM ACCESS STORAGE;

COMPUTER SIMULATION;

EID: 78149372184     PISSN: 1751858X     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cds.2010.0092     Document Type: Article

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