The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 1, 2008, Pages 86-97

  Agarwal, Kanak ^a,b   Nassif, Sani ^a,b  

^a IEEE   (United States)

^b IBM   (United States)

Author keywords

Memory; Noise; Process variation; SRAM; Stability; Yield

Indexed keywords

DEVICE PARAMETERS; PROCESS VARIATION; RANDOM DEVICE; ROBUSTNESS METRICS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; PARAMETER ESTIMATION; STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 37249034179     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.909792     Document Type: Article

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