An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 6, 2004, Pages 652-657

  Singh, Ravpreet ^a   Bhat, Navakanta ^b  

^a TEXAS INSTRUMENTS   (India)

^b INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

Process variation; Submicron technology; Transistor mismatch

Indexed keywords

DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; EXTRAPOLATION; FLIP FLOP CIRCUITS; MATHEMATICAL MODELS; MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE; VLSI CIRCUITS;

PROCESS VARIATION; SENSE AMPLIFIER ENABLE SIGNALS (SAEN); SUBMICRON TECHNOLOGY; TRANSISTOR MISMATCH;

AMPLIFIERS (ELECTRONIC);

EID: 3042566937     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.827566     Document Type: Review

References (13)

1. H. Shimuzu, K. Ijitsu, H. Akiyoshi, K. Aoyama, H. Takatsuks, K. Watanabe, R. Nanjo, and Y. Takao, "A 1.4 ns access 700 MHz 286 KB SRAM macro with expandable architecture," in ISSCC Dig. Tech. Papers, 1999, pp. 190-191.
2. B. Amrutur and M. A. Horowitz, "A replica technique for word line and sense control in low-power SRAMs," IEEE J. Solid-State Circuits, vol. 33, pp. 1208-1219, Aug. 1998.
3. S. J. Lovett, G. A. Gibbs, and A. Pancholy, "Yield and matching implications for static RAM memory array sense-amplifier design," IEEE J. Solid-State Circuits, vol. 35, pp. 1200-1204, Aug. 2000.
4. K. A. Bowman, X. Tang, J. C. Eble, and J. D. Meindl, "Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance," IEEE J. Solid-State Circuits, vol. 35, pp. 1186-1193, Aug. 2000.
5. A. J. Bhavnagarwala, X. Tang, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, pp. 658-665, Apr. 2001.
6. M. Eisele, J. Berthold, R. Thewes, E. Wohlrab, D. S-Landsiedel, and W. Weber, "Intra-die device parameter variation and their impact on digital CMOS gates at low-supply voltages," in IEDM Dig. Tech. Papers, 1995, pp. 67-70.
7. P. A. Stolk and D. M. Klaassen, "The effect of statistical dopant fluctuation on MOS device performance," in IEDM Dig. Tech. Papers, 1996, pp. 627-630.
8. K. Ishibashi, K. Takasugi, K. Komiyaji, H. Toyoshima, T. Yamanaka, A. Fukami, N. Hashimoto, N. Ohki, A. Shimizu, T. Hashimoto, T. Nagano, and T. Nishida, "A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers," IEEE J. Solid-State Circuits, vol. 30, pp. 480-486, Apr. 1995.
9. K. Seno, K. Knorpp, L.-L. Shu, N. Teshima, H. Kihara, H. Sato, F Miyaji, M. Takeda, M. Sasaki, Y. Tomo, T. Chuang, and K. Kobayashi, "A 9-ns 16 Mb CMOS SRAM with offset compensated current sense amplifier," IEEE J. Solid-State Circuits, vol. 28, pp. 1119-1123, Nov. 1993.
10. S. J. Lovett, "Threshold Voltage Mismatch Compensated Sense Amplifier for SRAM Memory Arrays," U.S. Patent 6 181 621, Jan. 30, 2001.
11. N. N. Wang, "On the design of MOS dynamic sense amplifiers," IEEE Trans. Circuits Syst., vol. CAS-29, pp. 467-477, July 1982.
12. H. Geib, W. Weber, and E. Wohlrab, "Experimental investigation of the minimum signal for reliable operation of DRAM sense amplifiers," IEEE J. Solid-State Circuits, vol. 27, pp. 1028-1035, July 1992.
13. W. T. Lynch and H. J. Boll, "Optimization of the latching pulse for dynamic flip-flop sensors," IEEE J. Solid-State Circuits, vol. SC-9, pp. 49-55, Apr. 1974.