Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 9, 2008, Pages 907-911

  Nho, Hyunwoo ^a   Yoon, Sei Seung ^b   Wong, S Simon ^a   Jung, Seong Ook ^c  

^a Stanford University   (United States)

^b QUALCOMM INC   (United States)

^c Yonsei University   (South Korea)

Author keywords

Monte Carlo; Process variations; SRAM; Yield

Indexed keywords

INTEGRATED CIRCUIT DESIGN; LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE;

ACCESS FAILURES; DESIGN VARIABLES; NUMERICAL ESTIMATION; PERIPHERY CIRCUITS; PROCESS VARIATION; STATISTICAL VARIATIONS; TRACKING SCHEME; YIELD;

MONTE CARLO METHODS;

EID: 51649125639     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.923411     Document Type: Article

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