A novel trapping/detrapping model for defect profiling in high-k materials using the two-pulse capacitance-voltage technique

IEEE Transactions on Electron Devices

Volumn 57, Issue 10, 2010, Pages 2726-2735

  Aguado, D Ruiz ^a,b   Govoreanu, B ^a   Zhang, W Dong ^b   Jurczak, M ^a   De Meyer, K ^a,c   Van Houdt, J ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c LIVERPOOL JOHN MOORES UNIVERSITY   (United Kingdom)

Author keywords

High k dielectrics; nonvolatile memories; semiconductor device modelling

Indexed keywords

BAND GAPS; CAPACITANCE VOLTAGE; CAPACITANCE-VOLTAGE TECHNIQUES; CHARACTERIZATION TECHNIQUES; DIELECTRIC CONSTANTS; ELECTRICAL PROPERTY; ELECTRICALLY ACTIVE DEFECTS; FLOATING-GATES; HIGH-K DIELECTRIC; HIGH-K MATERIALS; NONVOLATILE MEMORIES; PHYSICS-BASED MODELS; SEMICONDUCTOR DEVICE MODELLING; TRAPPING/DETRAPPING;

DEFECTS; ELECTRIC PROPERTIES; GATE DIELECTRICS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR SWITCHES;

DIELECTRIC MATERIALS;

EID: 77956989918     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2063292     Document Type: Article

References (28)

1. B. Govoreanu, D. P. Brunco, and J. Van Houdt, "Scaling down the interpoly dielectrics for next generation flash memory: Challenges and opportunities," Solid State Electron., vol.49, no.11, pp. 1841-1847, Nov. 2005.
2. M. van Duuren, R. van Schaijk, M. Slotboom, P. Tello, P. Goarin, N. Akil, F. Neuilly, Z. Rittersma, and A. Huerta, "Performance and reliability of 2-transistor FN/FN Flash arrays with Hafnium based high-k inter-poly dielectrics for embedded NVM," in Proc. NVSM Workshop, 2006, pp. 48-49.
3. D. Wellekens, P. Blomme, B. Govoreanu, J. De Vos, L. Haspeslagh, J. Van Houdt, D. P. Brunco, and K. van der Zanden, " Al2O3-based Flash interpoly dielectrics: A comparative retention study," in Proc. ESSDERC, 2006, pp. 238-241.
4. W. J. Zhu, T. Tamagawa, M. Gibson, T. Furukawa, and T. P. Ma, "Effect of Al inclusion in HfO2 on the physical and electrical properties of the dielectrics," IEEE Electron Device Lett., vol.23, no.11, pp. 649-651, Nov. 2002.
5. R. Degraeve, A. Kerber, P. Roussell, E. Cartier, T. Kauerauf, L. Pantisano, and G. Groeseneken, "Effect of bulk trap density on HfO2 reliability and yield," in IEDM Tech. Dig., 2003, pp. 38.5.1-38.5.4.
6. F. Crupi, R. Degraeve, A. Kerber, D. H. Kwak, and G. Groeseneken, "Correlation between stress-induced leakage current (SILC) and the HfO2 bulk trap density in a SiO2/HfO2 stack," in Proc. 42nd Annu. IEEE Int. Rel. Phys. Symp., 2004, pp. 181-187.
7. C. D. Young, D. Heh, S. V. Nadkarni, R. Choi, J. J. Peterson, J. Barnett, B. H. Lee, and G. Bersuker, "Electron trap generation in high-k gate stacks by constant voltage stress," IEEE Trans. Device Mater. Rel., vol.6, no.2, pp. 123-131, Jun. 2006. (Pubitemid 44304117)
8. J. F. Zhang, C. Z. Zhao, M. B. Zahid, G. Groeseneken, R. Degraeve, and S. de Gendt, "An assessment of the location of as-grown electron traps in HfO2/HfSiO stacks," IEEE Electron Device Lett., vol.27, no.10, pp. 817-820, Oct. 2006.
9. D. Heh, C. D. Young, G. A. Brown, Y. Hung, A. Diebold, G. Bersuker, E. M. Vogel, and J. B. Bernstein, "Spatial distributions of trapping centers in HfO2/SiO2 gate stacks," Appl. Phys. Lett., vol.88, no.15, p. 152 907, Apr. 2006.
10. A. Arreghini, F. Driussi, D. Esseni, L. Selmi, M. J. van Duuren, and R. van Schaijk, "New charge pumping model for the analysis of the spatial trap distribution in the nitride layer of SONOS devices," Microelectron. Eng., vol.80, no.1, pp. 333-336, Jun. 2005.
11. M. B. Zahid, R. Degraeve, L. Pantisano, J. F. Zhang, and G. Groeseneken, "Defects generation in SiO2/HfO2 studied with variable Tcharge Tdischarge charge pumping (VT2CP)," in Proc. IRPS, 2007, pp. 55-60.
12. Y. Wang, V. Lee, and K. P. Cheung, "Frequency dependent charge-pumping, how deep does it probe?" in IEDM Tech. Dig., 2006, pp. 1-4.
13. R. Degraeve, M. Cho, B. Govoreanu, B. Kaczer, M. B. Zahid, J. Van Houdt, M. Jurczak, and G. Groeseneken, "Trap spectroscopy by charge injection and sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks," in IEDM Tech. Dig., 2008, pp. 1-4.
14. C. D. Young, Y. Zhao, D. Heh, R. Choi, B. H. Lee, and G. Bersuker, "Pulsed Id-Vg methodology and its application to electron-trapping characterization and defect density profiling," IEEE Trans. Electron Devices, vol.56, no.6, pp. 1322-1329, Jun. 2009.
15. W. D. Zhang, B. Govoreanu, X. F. Zheng, D. Ruiz Aguado, M. Rosmeulen, P. Blomme, J. F. Zhang, and J. Van Houdt, "Two-pulse C-V : A new method for characterizing electron traps in the bulk of SiO2/high dielectric stacks," IEEE Electron Device Lett., vol.29, no.9, pp. 1043-1046, Sep. 2008.
16. H. Y. Yu, N. Wu, M. F. Li, C. Zhu, and B. J. Cho, "Thermal stability of (HfO2)x(Al2O3)1x on Si," Appl. Phys. Lett., vol.81, no.19, pp. 3618-3620, 2002.
17. D. Dictus, D. Shamiryan, V. Paraschiv, W. Boullart, S. De Gendt, and S. Vanhaelemeersch, "Influence of crystallographic orientation on dryetch properties of TiN," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol.24, no.5, pp. 2472-2476, Sep./Oct. 2006.
18. M. Rosmeulen, E. Sleeckx, and K. De Meyer, "Electrical characterization of silicon-rich-oxide-based memory cells using pulsed currentvoltage techniques," in Proc. Eur. Solid-State Device Res. Conf., 2002, pp. 471-474.
19. B. Govoreanu, D.Wellekens, L. Haspeslagh, J. De Vos, and J. Van Houdt, "Investigation of the low-field leakage through high-k interpoly dielectric stacks and its impact on nonvolatile memory data retention," in IEDM Tech. Dig., 2006, pp. 1-4.
20. A. Schenk and G. Heiser, "Modeling and simulation of tunneling through ultra-thin gate dielectrics," J. Appl. Phys., vol.81, no.12, pp. 7900-7908, Jun. 1997.
21. B. H. Bransden and C. J. Joachain, Introduction to Quantum Mechanics. White Plains, NY: Longman, 1989.
22. I. Lundstrom and C. Svensson, "Tunneling to traps in insulators," J. Appl. Phys., vol.43, no.12, pp. 5045-5047, Dec. 1972.
23. F. P. Heiman and G. Warfield, "The effects of oxide traps on the MOS capacitance," IEEE Trans. Electron Devices, vol.ED-12, no.4, pp. 167-178, Apr. 1965.
24. Y. Wang and M. H. White, "An analytical retention model for SONOS nonvolatile memory devices in the excess electron state," Solid State Electron., vol.49, no.1, pp. 97-107, Jan. 2005.
25. B. Govoreanu, R. Degraeve, J. Van Houdt, and M. Jurczak, "Statistical investigation of the floating gate memory cell leakage through high-k interpoly dielectrics and its impact on scalability and reliability," in IEDM Tech. Dig., 2008, pp. 1-4.
26. B. Govoreanu and J. Van Houdt, "On the roll-off of the activation energy plot in high-temperature Flash memory retention tests and its impact on the reliability assessment," IEEE Electron Device Lett., vol.29, no.2, pp. 177-179, Feb. 2008.
27. D. A. Buchanan,M. V. Fischetti, and D. J. DiMaria, "Coulombic and neutral trapping centers in silicon dioxide," Phys. Rev. B, Condens. Matter, vol.43, no.2, pp. 1471-1486, Jan. 1991.
28. E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi, N. Akil, M. J. van Duuren, and D. Golubovic, "Experimental and simulation analysis of program/retention transients in silicon nitride-based NVM cells," IEEE Trans. Electron Devices, vol.56, no.9, pp. 1980-1990, Sep. 2009.