Statistical investigation of the floating gate memory cell leakage through high-k interpoly dielectrics and its impact on scalability and reliability

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Govoreanu, B ^a   Degraeve, R ^a   Van Houdt, J ^a   Jurczak, M ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CELL LEAKAGES; FAILURE RATES; FLOATING GATE MEMORY CELLS; FLOATING GATES; HIGH TEMPERATURES; INTER POLY DIELECTRICS; LEAKAGE PATHS; MATERIAL PARAMETERS; MEMORY ARRAYS; MONTE-CARLO; STATISTICAL APPROACHES; TRAP DISTRIBUTIONS;

ELECTRON DEVICES; EXTRACTION; FLASH MEMORY; SCALABILITY;

GATE DIELECTRICS;

EID: 64549084894     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796692     Document Type: Conference Paper

References (7)

1. Semic. Int. Assoc. (SIA), Int. Tech. Roadmap Semic., ed. 2007.
2. B. Govoreanu et al Solid-St. Electron. 49(11): 1841-1848, 2005.
3. A. Kerber et al, J. Appl. Phys. 94(10): 6627-6630, 2003.
4. B. Govoreanu et al, IEDM Tech. Dig, pp. 479482, 2006.
5. R. Degraeve et al, IEDM Tech. Dig, 2008 (this conf).
6. R. Entner et al, Proc. SISPAD, pp. 219-222, 2005.
7. B. Govoreanu et al, Solid-St. Electron. 52(4): 557-563, 2008.