Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2010, Pages 107-114

  Dotan, Yocheved ^a   Chen, Orgad ^a   Katz, Gil ^a   Lilja, David J ^b  

^a RUPPIN ACADEMIC CENTER   (Israel)

^b University of Minnesota   (United States)

Author keywords

Combinational logic fault tolerance; Computer reliability; Fault tolerance; Logic design; Nanotechnology

Indexed keywords

CIRCUIT TECHNOLOGY; CMOS DEVICES; COMBINATIONAL LOGIC; DEEP SUB-MICRON; DRIVE CHARACTERISTIC; DYNAMIC FAULTS; ERROR CORRECTING CODE; FABRICATION TECHNIQUE; FAULT COVERAGES; FAULT RATES; FAULT-TOLERANT; GATE LEVELS; LOOK UP TABLE; NANO-COMPUTING; NANO-METER-SCALE; NANOSCALE DEVICE; RANDOM GATES;

COMPUTER ARCHITECTURE; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC DESIGN; NANOTECHNOLOGY; TABLE LOOKUP;

QUALITY ASSURANCE;

EID: 77955868179     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2010.5540775     Document Type: Conference Paper

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