Dynamic testing of xilinx virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

IEEE Transactions on Nuclear Science

Volumn 51, Issue 6 II, 2004, Pages 3469-3474

  Swift, Gary M ^a   Rezgui, Sana ^b   George, Jeffrey ^c   Carmichael, Carl ^b   Napier, Matthew ^d   Maksymowicz, John ^c   Moore, Jason ^b   Lesea, Austin ^b   Koga, R ^c   Wrobel, T F ^d  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b XILINX INC   (United States)

^c AEROSPACE CORPORATION   (United States)

^d SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

Fault injection; Radiation effects; Reconfigurable field programmable gate arrays (FPGAs); Single event effects

Indexed keywords

COSMIC RAYS; DATA ACQUISITION; ELECTRIC FAULT CURRENTS; LIGHT; NATURAL RESOURCES EXPLORATION; RADIATION EFFECTS; SENSITIVITY ANALYSIS; TESTING;

FAULT INJECTION; INPUT/OUTPUT BLOCK (IOB); REGULAR CONFIGURATION; SINGLE-EVENT EFFECTS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 19944370443     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.839190     Document Type: Conference Paper

References (12)

1. C. Yui, G. Swift, and C. Carmichael, "Single event upset susceptibility testing of the xilinx virtex IIFPGA," in Int. Conf. Military and Aerospace Applications of Programmable Logic Dev., Sept. 2002.
2. C. Yui, G. Swift, C. Carmichael, R. Koga, and J. George, "SEU mitigation testing of Xilinx Virtex II FPGAs," in Radiation Effects Data Workshop Record, 2003, pp. 92-97.
3. R. Koga, J. George, G. Swift, C. Yui, C. Carmichael, T. Langley, P. Murray, K. Lanes, and M. Napier, "Comparison of Xilinx Virtex-II FPGAs SEE sensitivities to protons and heavy ions," in Proc. 7th Eur. Conf. Radiation and Its Effects on Components and Systems, Sept. 2003.
4. T. Delong, B. Johnson, and J. Profeta, "A fault injection technique for VHDL behavioral-level models," IEEE Des. Test Comput., vol. 13, pp. 24-33, Winter 1996.
5. F. Lima, C. Carmichael, J. Fabula, R. Padovani, and R. Reis, "A fault injection analysis of Virtex FPGA TMR design methodology," in Proc. 6th Eur. Conf. Radiation and Its Effects on Components and Systems, Sept. 2001, pp. 275-282.
6. L. Antoni, R. Leveugle, and B. Feher, "Using run-time reconfiguration for fault injection applications," IEEE Trans. Instrum. Meas., vol. 52, no. 5, Oct. 2003.
7. M. Caffrey, P. Graham, E. Johnson, and M. Wirthlin, "Single-event upsets in SRAM FPGAs," in Int. Conf. Military and Aerospace Applications of Programmable Logic Devices, Sept. 2002.
8. M. Alderighi, F. Casini, S. D'angelo, M. Mancini, A. Marmo, S. Pastore, and G. Sechi, "A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx Virtex FPGAs," in Proc. 18th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Nov. 2003.
9. G. Swift, C. Yui, and C. Carmichael, "Mitigating upsets in SRAM-based FPGAs from the xilinx virtex 2 family," in Int. Conf. Military and Aerospace Applications of Programmable Logic Devices, Sept. 2003.
10. P. Graham, M. Caffrey, M. Wirthlin, E. Johnson, and N. Rollins, "SEU mitigation for half-latches in xilinx virtex FPGAs," IEEE Trans. Nucl. Sci., vol. 50, pp. 2139-2146, Dec. 2003.
11. P. Sundararajan, C. Patterson, C. Carmichael, S. McMillan, and B. Blodget, "Estimation of single event upset probability impact of FPGA designs," in Int. Conf. Military and Aerospace Applications of Programmable Logic Devices, Sept. 2003.
12. C. Carmichael. (2001, Nov.) Triple module redundancy design techniques for Virtex FPGAs. Xilinx Application Note XAPP197 [Online]. Available: www.xilinx.com/bvdocs/appnotes/xapp197.pdf