A system architecture solution for unreliable nanoelectronic devices

IEEE Transactions on Nanotechnology

Volumn 1, Issue 4, 2002, Pages 201-208

  Han, Jie ^a   Jonker, Pieter ^a,b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b IEEE   (Netherlands)

Author keywords

Computer architecture; Fault tolerance; Markov processes; Multiplexing; Nanotechnology; Stochastic system

Indexed keywords

FAULT-TOLERANT ARCHITECTURES; NAND MULTIPLEXING TECHNIQUE; STOCHASTIC SYSTEM;

COMPUTER ARCHITECTURE; ELECTRON TUNNELING; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUITS; MULTIPLEXING; NANOTECHNOLOGY;

ELECTRONIC EQUIPMENT;

EID: 0012223405     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2002.807393     Document Type: Conference Paper

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