Exploring fine-grained fault tolerance for nanotechnology devices with the recursive nanobox processor grid

IEEE Transactions on Nanotechnology

Volumn 5, Issue 5, 2006, Pages 575-586

  Kleinosowski, A J ^b,c   Pai, Vasudev V ^b,d   Rangarajan, Vijay ^b,e   Ranganath, Priyadarshini ^b,f   Kleinosowski, Kevin ^b   Subramony, Mahesh ^b   Lilja, David J ^a,b  

^a IEEE

^b UNIVERSITY OF MINNESOTA   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

^d MARVELL SEMICONDUCTOR INC   (United States)

^e ADVANCED MICRO DEVICES   (United States)

^f INTEL CORPORATION   (United States)

Author keywords

Computer architecture; Fault tolerance; Logic design; Nanotechnology; Robustness

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; LOGIC DESIGN; NANOTECHNOLOGY; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS; RANDOM ERRORS; TABLE LOOKUP;

ENCODED LOOKUP TABLES; MOLECULAR NANOTECHNOLOGY; NANOBOX PROCESSOR CELL;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 33749029005     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2006.880901     Document Type: Article

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