Combining static and dynamic defect-tolerance techniques for nanoscale memory systems

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 773-778

  Biswas, Susmit ^a   Wang, Gang ^a   Metodi, Tzvetan S ^b   Kastner, Ryan ^a   Chong, Frederic T ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CODES (STANDARDS); CODES (SYMBOLS); DEFECTS; DESIGN; ERROR ANALYSIS; LEARNING SYSTEMS; MAPS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; VIDEO STREAMING;

BIT ERRORS; COARSE-GRANULARITY; COMPUTER-AIDED DESIGN; DEFECT-TOLERANCE; DEVICE DENSITY; DYNAMIC ERRORS; ERROR CORRECTION CODES; ERROR RATES; FILTER-BASED; INTERNATIONAL CONFERENCES; MEMORY EFFICIENCY; NANOSCALE MEMORIES; NANOSCALE TECHNOLOGIES; STATIC AND DYNAMIC; VIRTUAL MEMORY;

ERROR CORRECTION;

EID: 50249169953     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397359     Document Type: Conference Paper

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