A 2.4-GHz low-power all-digital phase-locked loop

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 8, 2010, Pages 1513-1521

  Xu, Liangge ^a   Lindfors, Saska ^b   Stadius, Kari ^a   Ryynänen, Jussi ^a  

^a AALTO UNIVERSITY   (Finland)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

ADPLL; DCO; frequency synthesis; ISM band; low power; TDC; variable phase accumulator

Indexed keywords

ACTIVE AREA; ADAPTIVE GAIN; ALL DIGITAL PHASE LOCKED LOOP; AVERAGE POWER; DELAY LINE; DIGITALLY CONTROLLED LC OSCILLATORS; DIRECT FREQUENCY MODULATION; FEEDBACK PATHS; FREQUENCY SYNTHESIS; HIGH-SPEED; ISM BANDS; LOW DUTY-CYCLES; LOW POWER; POWER CONSUMPTION; REFERENCE SIGNALS; TIME TO DIGITAL CONVERTERS; TWO-POINT MODULATION; VARIABLE PHASE;

DELAY CIRCUITS; FREQUENCY CONVERTERS; FREQUENCY MODULATION; PHASE NOISE; POSITION MEASUREMENT;

PHASE LOCKED LOOPS;

EID: 77955132112     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2047453     Document Type: Conference Paper

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