A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 10, 2009, Pages 2808-2816

  Lee, Minjae ^a   Heidari, Mohammad E ^b   Abidi, Asad A ^c  

^a AGILENT TECHNOLOGIES   (United States)

^b BROADCOM CORPORATION   (United States)

^c Engineering IV   (United States)

Author keywords

Coarse fine architecture; Digital phase locked loop; Time amplifier; Time to digital converter (TDC); Wideband modulation

Indexed keywords

COARSE-FINE ARCHITECTURE; DIGITAL PHASE-LOCKED LOOP; TIME AMPLIFIER; TIME-TO-DIGITAL CONVERTER (TDC); WIDEBAND MODULATION;

AMPLIFICATION; BROADBAND AMPLIFIERS; DELAY CIRCUITS; FREQUENCY CONVERTERS; INSTRUMENT SCALES; PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 70350592003     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2028753     Document Type: Article

References (17)

1. M. E. Heidari, M. Lee, and A. A. Abidi, "All digital outphasing modulator for software defined radio," in Proc. Symp. VLSI Circuits, Jun. 2008, pp. 98-99.
2. R. B. Staszewski et al., "All-digital TX frequency synthesizer and discrete- time receiver for bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol.39, no.12, pp. 2278-2291, Dec. 2004.
3. R. B. Staszewski, C.-M. Hung, N. Barton, M.-C. Lee, and D. Leipold, "A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones," IEEE J. Solid-State Circuits, vol.40, no.11, pp. 2203-2211, Nov. 2005.
4. R. Tonietto, E. Zuffetti, and R. Castello, "A 3 MHz bandwidth low noise RF all digital PLL with 12 ps resolution time-to-digital converter," in Proc. ESSCIRC, Sep. 2006, pp. 150-153.
5. S. Pamarti, L. Jansson, and I. Galton, "A wideband 2.4-GHz deltasigma fractional- PLL with 1-Mb/s in-loop modulation," IEEE J. Solid-State Circuits, vol.39, no.11, pp. 49-52, Nov. 2004.
6. R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, "TDC-based frequency synthesizer for wireless applications," in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., Jun. 2004, pp. 215-218.
7. R. B. Staszewski et al., "All-digital PLL and GSM/EDGE transmitter in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 316-317.
8. S. E. Meninger and M. H. Perrott, "A 1-MHz bandwidth 3.6-GHz 0.18 μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise," IEEE J. Solid-State Circuits, vol.41, no.4, pp. 966-980, Apr. 2006.
9. C.-M. Hsu, M. Z. Strayer, and M. H. Perrott, "A low-noise, wide-BW 3.6 GHz digital fractional- synthesizer with a noise-shaping time-to digital converter and quantization noise cancellation," IEEE J. Solid-State Circuits, vol.43, no.12, pp. 2776-2786, Dec. 2008.
10. M. Lee and A. A. Abidi, "A 9b 1.25 ps resolution coarse-fine time-todigital converter in 90 nmCMOSthat amplifies a time residue," in Proc. Symp. VLSI Circuits, Jun. 2007, pp. 168-169.
11. M. Lee and A. A. Abidi, "A 9b 1.25 ps resolution coarse-fine time-todigital converter in 90 nm CMOS that amplifies a time residue," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 769-777, Apr. 2008.
12. R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, 1 ed. New York: Wiley-Interscience, 2006.
13. R. B. Staszewski, S. Vemulapalli, P. Vallur, J.Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II, vol.53, no.3, pp. 220-224, Mar. 2006.
14. C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, "A 3 GHz fractional- N all-digital PLL with precise time-to-digital converter calibration and mismatch correction," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2008, pp. 344-345.
15. M. Lee and A. A. Abidi, "A low noise wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution," in Proc. Symp. VLSI Circuits, Jun. 2008, pp. 112-113.
16. M. E. Heidari, M. Lee, and A. A. Abidi, "All digital outphasing modulator for software defined radio," IEEE J. Solid-State Circuits, vol.44, no.4, pp. 1260-1270, Apr. 2009.
17. E. Temporiti, C. Weltin-Wu, D. Baldi, R. Tonietto, and F. Svelto, "A 3 GHz fractional-N all-digital PLL with a 1.8 GHz bandwidth implementing spur reduction techniques," IEEE J. Solid-State Circuits, vol.44, no.3, pp. 824-834, Mar. 2009.