A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 10, 2009, Pages 2808-2816

  Lee, Minjae ^a   Heidari, Mohammad E ^b   Abidi, Asad A ^c  

^a AGILENT TECHNOLOGIES   (United States)

^b BROADCOM CORPORATION   (United States)

^c Department of Civil and Environmental Engineering   (United States)

Author keywords

Coarse fine architecture; Digital phase locked loop; Time amplifier; Time to digital converter (TDC); Wideband modulation

Indexed keywords

COARSE-FINE ARCHITECTURE; DIGITAL PHASE-LOCKED LOOP; TIME AMPLIFIER; TIME-TO-DIGITAL CONVERTER (TDC); WIDEBAND MODULATION;

AMPLIFICATION; BROADBAND AMPLIFIERS; DELAY CIRCUITS; FREQUENCY CONVERTERS; INSTRUMENT SCALES; PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 70350592003     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2028753     Document Type: Article

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