TDC-based frequency synthesizer for wireless applications

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2004, Pages 215-218

  Staszewski, Robert Bogdan ^a   Leipold, Dirk ^a   Hung, Chih Ming ^a   Balsara, Poras T ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

All digital PLL; Bluetooth; GSM; Phase detector; Phase socked loop; Time to digital converter

Indexed keywords

ALL-DIGITAL PHASE LOCKED LOOPS (PLL); BLUETOOTH; PHASE DETECTORS; TIME-TO-DIGITAL CONVERTERS; WIRELESS APPLICATIONS;

ACOUSTIC NOISE; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC POTENTIAL; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; THERMAL EFFECTS; TRANSISTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

FREQUENCY SYNTHESIZERS;

EID: 4444331072     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. R. B. Staszewski, C-M Hung, D. Leipold and P. T. Balsara, "A first multigigahertz digitally controlled oscillator for wireless applications," IEEE Trans. on Microwave Theory and Techniques, vol. 51, no. 11, pp. 2154-2164, Nov. 2003.
2. R. B. Staszewski, D. Leipold, K Muhammad and P. T. Balsara, "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process," IEEE Trans. on Circuits and Systems II, vol. 50, no. 11, pp. 815-828, Nov. 2003
3. B. Staszewski, C-M. Hung, K. Maggio, J. Wallberg, D. Leipold and P. Balsara, "All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13μm CMOS," Proc. of IEEE Solid-State Circuits Conf., sec. 15.3, pp. 272-273, 527, Feb. 2004
4. P. Dudek, S. Szczepanski and J. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
5. T. Riley, N. Filiol, Q. Du and J. Kostamovaara, "Techniques for in-band phase noise reduction in σΔ synthesizers," IEEE Trans on Circuits and Systems II, vol. 50, no. 11, pp. 794-803, Nov. 2003.