Designs of counters with near minimal counting/sampling period and hardware complexity

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2000, Pages 894-898

  Yeh, C H ^a   Parhami, B ^a   Wang, Y ^a  

^a QUEEN S UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COST EFFECTIVENESS; DATA COMMUNICATION SYSTEMS; DESIGN FOR TESTABILITY; FLIP FLOP CIRCUITS; SAMPLING;

SYNCHRONOUS COUNTERS;

COUNTING CIRCUITS;

EID: 0034441923     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)