A 3 GHz fractional all-digital pLL with a 1.8 MHz bandwidth implementing spur reduction techniques

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 3, 2009, Pages 824-834

  Temporiti, Enrico ^a   Weltin Wu, Colin ^b   Baldi, Daniele ^a   Tonietto, Riccardo ^c   Svelto, Francesco ^d  

^a STMICROELECTRONICS   (Italy)

^b Och Spine at New York Presbyterian Hospitals   (United States)

^c STMICROELECTRONICS   (France)

^d UNIVERSITY OF PAVIA   (Italy)

Author keywords

ADPLL; All digital phase locked loop; Digital calibration; Fractional frequency synthesizer; Mismatch correction; Spur reduction; Time to digital converter (TDC); Vernier TDC

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CALIBRATION; CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; FREQUENCY SYNTHESIZERS; PHASE SHIFT; TELECOMMUNICATION SYSTEMS;

ADPLL; ALL-DIGITAL PHASE LOCKED LOOP; DIGITAL CALIBRATION; FRACTIONAL FREQUENCY SYNTHESIZER; MISMATCH CORRECTION; SPUR REDUCTION; TIME-TO-DIGITAL CONVERTER (TDC); VERNIER TDC;

PHASE LOCKED LOOPS;

EID: 61449204062     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2012363     Document Type: Article

References (16)

1. P. R. Westlake, "Digital phase control techniques," IRE Trans. Commun. Syst., vol. 8, no. 4, pp. 237-246, Dec. 1960.
2. W. C. Lindsey and C. M. Chie, "A survey of digital phase-locked loops," Proc. IEEE, vol. 69, no. 4, pp. 410-131, Apr. 1981.
3. R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, "TDC-based frequency synthesizer for wireless applications," in 2004 IEEE Radio Frequency Integrated Circuits Symp. Dig., pp. 215-218.
4. R. B. Staszewski, C.-M. Hung, N. Barton, M.-C. Lee, and D. Leipold, "A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2203-2211, Nov. 2005.
5. C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, "A 3 GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction," in 2008 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 344-345.
6. M. Ferriss and M. P. Flynn, "A 14 mW fractional-N PLL modulator with an enhanced digital phase detector and frequency switching scheme," in 2007 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 352-353.
7. C.-M. Hsu, M. Z. Straayer, and M. H. Perrott, "A low-noise, wide-BW 3.6 GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation," in 2008 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 340-341.
8. V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, "A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy," IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 54, no. 3, pp. 247-251, Mar. 2007.
9. A. Swaminathan, A. Panigada, E. Masry, and I. Galton, "A digital requantizer with shaped requantization noise that remains well behaved after nonlinear distortion," IEEE Trans. Signal Process., vol. 55, no. 11, pp. 5382-5394, Nov. 2007.
10. E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, "A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for wcdma applications," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1446-1454, Sep. 2004.
11. R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 54, no. 3, pp. 220-224, Mar. 2006.
12. U. Vollenbruch, Y. Liu, T. Bauernfeind, T. Pittorino, V. Neubauer, T. Mayer, and L. Maurer, "Requirements for time-to-digital converters in the context of digital-PLL based frequency synthesis and GSM modulation," in Proc. 2006 IEEE Microwave Srmp., pp. 1817-1820.
13. B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, "A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance." IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855-863, Apr. 2008.
14. P. Dudek, S. Szczepanski, and J. V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a vernier delay line," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-246, Feb. 2000.
15. J. Rivoir, "Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator," in Proc. 2006 IEEE Asian Test Symp., pp. 45-50.
16. J. Doernberg, H.-S. Lee, and D. A. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol. SSC-19, no. 6, pp. 820-827, Dec. 1984.