High-speed digital circuits for a 2.4 GHZ all-digital RF frequency synthesizer in 130 NM CMOS

Proceedings of the 2004 IEEE Dallas/CAS Workshop: Implementation of High Performance Circuits. DCAS-04

Volumn , Issue , 2004, Pages 167-170

  Staszewski, Robert B ^a   Wallberg, John ^a   Koh, Jinseok ^a   Balsara, Poras T ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; FABRICATION; GATES (TRANSISTOR); MOBILE TELECOMMUNICATION SYSTEMS; NATURAL FREQUENCIES; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; SPECIFICATIONS; WIRELESS TELECOMMUNICATION SYSTEMS;

ALL-DIGITAL RF FREQUENCY SYNTHESIZER; BLUETOOTH; HIGH-SPEED DIGITAL CIRCUITS; PHASE DETECTORS; TIME-TO-DIGITAL CONVERTERS (TDC);

DIGITAL CIRCUITS;

EID: 16244367743     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dcas.2004.1360452     Document Type: Conference Paper

References (8)

1. R. B. Staszewski, C-M Hung, D. Leipold, and P. T. Balsara, "A first multigigahertz digitally controlled oscillator for wireless applications," IEEE Trans. on Microwave Theory and Techniques, vol. 51, no. 11, pp. 2154-2164, Nov. 2003.
2. R. B. Staszewski, D. Leipold, K Muhammad, and P. T. Balsara, "Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process," IEEE Trans. on Circuits and Systems II, vol. 50, no. 11, pp. 815-828, Nov. 2003.
3. R. B. Staszewski, R. Staszewski, J. Wallberg, T. Jung, C-M Hung, D. Leipold, K. Maggio, and P. T. Balsara, "DSP-coupled 2.4 GHz RF transmitter in 130 nm CMOS," Proc. of 2004 IEEE Dallas CAS Workshop on Implementation of High Performance Circuits., sec. xx-x, pp. xx-xx, Sept. 2004.
4. R. E. Best, Phase Locked Loops: Design, Simulation and Applications, second edition. New York, NY: McGraw-Hill, 1993.
5. B. N. Nikolic, V. G. Oklobdzija, V. Stajonovic et al., "Improved sense-amplifier-based flip-flop: design and measurements," IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 876-884, June 2000.
6. R. B. Staszewski, K. Muhammad, and P. Balsara, "A 550-MSample/s 8-tap FIR digital filter for magnetic recording read channels," IEEE Journal of Solid-State Circuits, vol. 35, iss. 8, pp. 1205-1210, Aug. 2000.
7. "GS40 0.11 -μm CMOS Standard Cell/Gate Array," Texas Instruments Application Specific Integrated Circuits Macro Library Summary, Version 1.0, Jan. 2001.
8. T. J. Gabara, G. J. Cyr, C. E. Stroud, "Metastability of CMOS master/slave flip-flops," IEEE Trans. on Circuits and Systems-II, vol. 39, no. 10, pp. 734-740, Oct. 1992.