A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2842-2850

  Gupta, Manoj ^b   Song, Bang Sup ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Delta sigma modulation; Fractional N frequency synthesizers; Phase locked loops; Spur cancellation

Indexed keywords

CHARGE PUMP; GAIN MATCHING; LEAST MEAN SQUARE; PHASE NOISE; SPUR CANCELLATION;

BROADBAND NETWORKS; CALIBRATION; FREQUENCY SYNTHESIZERS; GAIN MEASUREMENT; LEAST SQUARES APPROXIMATIONS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE;

ANALOG TO DIGITAL CONVERSION;

EID: 33845663553     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884829     Document Type: Conference Paper

References (24)

1. M. Perrott, T. Tewksbury, and C. Sodini, "A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2048-2060, Dec. 1997.
2. W. Rhee, A. Ali, and B. Song, "A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3-bit 3rd-order delta-sigma modulator," in IEEE ISSCC Dig. Tech. Papers, 2000, pp. 198-199.
3. B. De Muer and M. S. J. Steyaert, "On the analysis of delta-sigma fractional-N frequency synthesizers for high spectral purity," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 784-793, Nov. 2003.
4. S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation. New York: IEEE Press, 1997.
5. B. De Muer and M. S. J. Steyaert, "A CMOS monolithic delta-sigma-controlled fractional-N frequency synthesizer for DCS-1800," IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 835-844, Jul. 2002.
6. J. Craninckx and M. S. J. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthesizer," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, Dec. 1998.
7. B. Miller and R. Conley, "A multiple modulator fractional divider," IEEE Trans. Instrum. Meas., vol. 40, no. 3, pp. 578-583, Jun. 1991.
8. T. Riley, M. Copeland, and T. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993.
9. G. Gillette, "Digiphase synthesizer," in Proc. 23rd Annu. Frequency Control Symp., 1969, pp. 201-210.
10. W. Rhee and A. Ali, "An on-chip compensation technique in fractional-N frequency synthesis," in Proc. IEEE Int. Symp. Circuits and Systems, 1999, pp. 363-366.
11. I. Bietti, E. Ternporitil, G. Albasini, and R. Castello, "An UMTS SD fractional synthesizer with 200 kHz bandwidth and - 128 dBc/Hz @1 MHz using spurs compensation and linearization techniques," in IEEE Custom Integrated Circuits Conf., 2003, pp. 463-466.
12. S. Meninger and M. Perrott, "A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 839-849, Nov. 2003.
13. S. Pamarti, L. Jansson, and I. Galton, "A wideband 2.4 GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 49-62, Jan. 2004.
14. Y. Dufour, "Method and apparatus for performing fractional division charge compensation in a frequency synthesizer," U.S. Patent 6,130,561, Oct. 10, 2000.
15. Y. Koo et al., "A fully integrated frequency synthesizer with charge-averaging charge pump and dual path loop filter fro PCS and cellular CDMA wireless systems," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002.
16. S. Pellerano et al., "A dual band frequency synthesizer for 802.11 a/b/g with fractional spur averaging technique," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 20-22.
17. S. Dasgupta et al., "Sign-sign LMS convergence with independent stochastic inputs," IEEE Trans. Inf. Theory, vol. 36, no. 1, pp. 197-201, Jan. 1990.
18. D. Leeson, "A simple model of feedback oscillator noise spectrum," Proc. IEEE, vol. 54, no. 2, pp. 329-330, Feb. 1966.
19. A. Hajimiri and T. Lee, "Design issues in CMOS differential LC oscillators," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999.
20. J. Rael and A. Abidi, "Physical processes of phase noise in differential LC oscillators," in Proc. IEEE Custom Integrated Circuits Conf., 2000, pp. 569-572.
21. M. Danesh and J. Long, "Differentially driven symmetric microstrip inductors," IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 332-340, Jan. 2002.
22. R. Castello et al., "A metal oxide semiconductor varactor," IEEE Electron Device Lett., vol. 20, no. 4, pp. 164-166, Apr. 1999.
23. J. Cranickx and M. S. J. Steyaert, "A 1.75-GHz/3-V dual modulus divide-by- 128/129 prescaler in 0.7-μm CMOS," IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, Jul. 1996.
24. M. Gupta and B.-S. Song, "A 1.8GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 1922-1931.