A high-speed variable phase accumulator for an ADPLL architecture

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 1736-1739

  Xu, Liangge ^a   Lindfors, Saska ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; FREQUENCY DOMAIN ANALYSIS; NETWORKS (CIRCUITS); NONMETALS; PHASE LOCKED LOOPS; POSITION MEASUREMENT; SHIFT REGISTERS; SILICON; TECHNICAL PRESENTATIONS; TELECOMMUNICATION; TOPOLOGY;

ALL DIGITAL PHASE-LOCKED LOOP; CMOS PROCESSING; CRITICAL PATHS; FREQUENCY DOMAINS; HIGH SPEEDS; INTERNATIONAL SYMPOSIUM; POWER DISSIPATIONS; REFERENCE FREQUENCY; RF SIGNALS; SILICON AREA; SPEED INCREASING; VARIABLE PHASE;

SPEED;

EID: 51949118608     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541773     Document Type: Conference Paper

References (8)

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