Analyzing the soft error resilience of linear solvers on multicore multiprocessors

Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010

Volumn , Issue , 2010, Pages

  Malkowski, Konrad ^a   Raghavan, Padma ^a   Kandemir, Mahmut ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SCHEME; BIT-FLIPS; CACHE STRUCTURE; CHIP AREAS; CONJUGATE GRADIENT; ECC SCHEME; ENERGY CONSUMPTION; ITERATIVE SOLVERS; L2 CACHE; LINEAR SOLVER; MULTI CORE; MULTI-CORE PROCESSOR; SOFT ERROR; TRANSISTOR DENSITY;

CACHE MEMORY; CONJUGATE GRADIENT METHOD; DISTRIBUTED PARAMETER NETWORKS; ENERGY EFFICIENCY; ERROR CORRECTION; MULTIPROCESSING SYSTEMS;

MICROPROCESSOR CHIPS;

EID: 77953987800     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2010.5470411     Document Type: Conference Paper

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