A framework for correction of multi-bit soft errors in L2 caches based on redundancy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 2, 2009, Pages 194-206

  Bhattacharya, Koustav ^a   Ranganathan, Nagarajan ^a   Kim, Soontae ^b  

^a University of South Florida   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Control mine redundancy; Error detection and correction; L2 caches; Multi bit errors; Soft errors

Indexed keywords

BENCHMARKING; BIT ERROR RATE; CACHE MEMORY; CODES (SYMBOLS); ERROR CORRECTION; ERRORS; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; REDUNDANCY; RELIABILITY;

CONTROL/MINE REDUNDANCY; ERROR DETECTION AND CORRECTION; L2 CACHES; MULTI-BIT ERRORS; SOFT ERRORS;

ERROR DETECTION;

EID: 58949088869     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2003236     Document Type: Article

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