Computing cache vulnerability to transient errors and its implication

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 427-435

  Zhang, Wei ^a  

^a SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE VULNERABILITY; MICROPROCESSOR DESIGNS; TRANSIENT ERRORS; WRITE-BACK STRATEGIES;

BUFFER STORAGE; HIERARCHICAL SYSTEMS; MICROPROCESSOR CHIPS; RELIABILITY;

ERROR ANALYSIS;

EID: 28444436225     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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