Statistical path selection for at-speed test

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 624-631

  Zolotov, Vladimir ^a   Xiong, Jinjun ^a   Fatemi, Hanif ^b   Visweswariah, Chandu ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH-AND-BOUND ALGORITHMS; CHIP DESIGNS; DELAY CHANGES; FAULT MODELS; OPEN PROBLEMS; PARAMETRIC VARIATIONS; PATH SELECTIONS; PATH TRACINGS; PROCESS VARIATIONS; SPACE COVERAGES; SPEED TESTS;

INTEGRATED CIRCUITS;

COMPUTER AIDED DESIGN;

EID: 57849101587     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681642     Document Type: Conference Paper

References (12)

1. V. Iyengar, T. Yokota, K. Yamada, T. Anemikos, R. Bassett, M. Degregorio, R. Farmer, G. Grise, M. Johnson, D. Milton, M. Taylor, and F. Woytowich. At-speed structural test for high-performance ASICs. Proc. International Test Conference, pages 2.4:1-10, October 2006. Santa Clara, CA.
2. N. Tendolkar, R. Raina. R. Woltenberg, X. Lin, B. Swanson, and G. Aldrich. Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC instruction set architecture. IEEE VLSI Test Symposium, pages 3-8, April 2002. Monterey, CA.
3. V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. A. Habitz, and C. Visweswariah. Variation-aware performance verification using at-speed structural test and statistical timing. IEEE International Conference on Computer-Aided Design, November 2007. San Jose, CA.
4. M. L. Bushnell and V. D. Agrawal. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Kluwer Academic Publishers, 2000.
5. L-C. Wang, J-J. Liou, and K-T. Cheng. Critical path selection for delay fault testing based upon a statistical timing model. IEEE Transactions on Computer-Aided Design of ICs and Systems, 23(11): 1550-1565, November 2004.
6. M. Sharma and J. H. Patel. Finding a small set of longest testable paths that cover every gate. International Test Conference, pages 974-982, October 2002. Baltimore, MD.
7. |7] J-J. Liou. A. Krstic, L-C. Wang, and K-T. Cheng. False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. Proc. 2002 Design Automation Conference, pages 566-569, June 2002. New Orleans, LA.
8. W. Qiu and D. M. H. Walker. An efficient algorithm for finding k longest testable paths through each gate in a combinational circuit. International Test Conference, pages 592-601, Setpember 2003. Charlotte. NC.
9. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan. First-order incremental block-based statistical timing analysis. Proc. 2004 Design Automation Conference, pages 331-336, June 2004. San Diego, CA.
10. H. Chang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. IEEE International Conference on Computer-Aided Design, pages 621-625, November 2003. San Jose, CA.
11. D. J. Hathaway, J. P. Alvarez, and K. P. Belkhale. Network timing analysis method which eliminates timing variations between signals traversing a common circuit path. U. S. Patent 5,636,372, June 1997.
12. J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran. Criticality computation in parameterized statistical timing. Proc. 2006 Design Automation Conference, pages 63-68, July 2006. San Francisco, CA.