Statistical static timing analysis technology

Fujitsu Scientific and Technical Journal

Volumn 43, Issue 4, 2007, Pages 516-523

  Nitta, Izumi ^a,b   Shibuya, Toshiyuki ^a,c   Homma, Katsumi ^a,c  

^a FUJITSU LABORATORIES LTD   (Japan)

^b Information Processings Society (IPSJ) of Japan   (Japan)

^c Institute of Electronics   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY SCALING; DESIGN TURNAROUND TIME (TAT); STATISTICAL STATIC TIMING ANALYSIS TECHNOLOGY;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; STATISTICAL METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 36048954466     PISSN: 00162523     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. th Workshop on Circuits and Systems in Karuizawa, 2005, p.533-538.
2. A. Srivastava et al.: Statistical Analysis and Optimization for VLSI: Timing and Power. Springer, 2005.
3. H. Komatsu et al.: Statistical Timing Analysis and its Application to Microprocessor Design, (in Japanese), IPSJ Symposium Series, Vol. 2006, No.7, p.1-6.
4. I. Nitta et al.: A Study of the Model and the Accuracy of Statistical Timing Analysis, (in Japanese), IEICE Technical Report, VLD 2005-71, 105, 442, p.61-66 (2005).
5. K. Homma, et al.: A Study of the Execution Path Number and the Accuracy of Path-Based Statistical Timing Analysis, (in Japanese) IEICE Technical Report, CPSY2005-74, 105, 669, p.61-66 (2006).