Test-quality/cost optimization using output-deviation-based reordering of test patterns

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 2, 2008, Pages 352-364

  Wang, Zhanglei ^b   Chakrabarty, Krishnendu ^a,c  

^a IEEE

^b CISCO SYSTEMS   (United States)

^c USA   (United States)

Author keywords

Abort on first fail; Defect coverage; Test selection; Test application time; Test pattern grading

Indexed keywords

COST BENEFIT ANALYSIS; MATHEMATICAL MODELS; MICROMETERS; OPTIMIZATION; PATTERN RECOGNITION; PROBABILITY;

ABORT-ON-FIRST-FAIL; DEFECT COVERAGE; TEST SELECTION; TEST-APPLICATION TIME; TEST-PATTERN GRADING;

SPEED CONTROL;

EID: 38649125872     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.907228     Document Type: Article

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