Delay fault simulation with bounded gate delay model

Proceedings - International Test Conference

Volumn , Issue , 2007, Pages

  Bose, Soumitra ^a,c   Grimes, Hillary ^b   Agrawal, Vishwani D ^b  

^a INTEL CORPORATION   (United States)

^b AUBURN UNIVERSITY   (United States)

^c UBS Investment Bank   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; HAZARDS; MATHEMATICAL MODELS;

DELAY FAULT SIMULATION; GATE DELAY MODEL;

ELECTRIC DELAY LINES;

EID: 39749150488     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437637     Document Type: Conference Paper

References (25)