Automatic generation of instructions to robustly test delay defects in processors

Proceedings - 12th IEEE European Test Symposium, ETS 2007

Volumn , Issue , 2007, Pages 173-178

  Gurumurthy, Sankar ^a   Vemu, Ramtilak ^a   Abraham, Jacob A ^a   Saab, Daniel G ^b  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CACHE MEMORY; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS;

ATPG ENGINES; AUTOMATIC GENERATION; DELAY DEFECTS; DELAY FAULTS;

PROGRAM PROCESSORS;

EID: 34548809229     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2007.13     Document Type: Conference Paper

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