A new delay test based on delay Defect Detection within Slack Intervals (DDSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 11, 2006, Pages 1216-1226

  Yan, Haihua ^a,b   Singh, Adit D ^a,c  

^a IEEE   (United States)

^b SYNOPSYS INC   (United States)

^c AUBURN UNIVERSITY   (United States)

Author keywords

Digital circuits; VLSI

Indexed keywords

DEFECT DETECTION WITHIN SLACK INTERVALS (DDSI); LOGIC BLOCKS; SWITCHING DELAYS; TEST CHIPS;

COMPUTER SIMULATION; DIGITAL CIRCUITS; ELECTRIC FAULT LOCATION; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

DELAY CIRCUITS;

EID: 33845534431     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.886415     Document Type: Article

References (23)

1. A. Pierzynska and S. Pilarsky, "Non-robust versus robust," in Proc. Int. Test Conf., 1995, pp. 123-131.
2. E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testing," in Proc. 14th Des. Autom. Conf., 1977, pp. 462-468.
3. B. Dervisoglu and G. Strong, "Design for testability: Using scanpath techniques for path delay test and measurement," in Proc. IEEE Int. Test Conf., 1991, pp. 365-374.
4. J. Savir and S. Patil, "Broad-side delay test," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 13, no. 8, pp. 1057-1064, Aug. 1994.
5. J. L. Avra and E. J. McCluskey, "Synthesizing for scan dependence in built-in self-testable design," in Proc. Int. Test Conf., 1993, pp. 734-743.
6. P. Varma, "On path-delay testing in a standard scan environment," in Proc. Int. Test Conf., 1994, pp. 164-173.
7. J. Savir, "Scan latch design for delay test," in Proc. Int. Test Conf., 1997, pp. 446-453.
8. R. Tekumalla and P. Menon, "Delay testing with clock control: An alternative to enhanced scan," presented at the Int. Test Conf., Atlantic City, NJ, 1997.
9. E. J. McCluskey, "Can DFT totally delete traditional functional testing?," presented at the Int. Test Conf., Atlantic City, NJ, 2000.
10. B. Kruseman, A. K. Majhi, G. Gronthoud, and S. Eichenberger, "On hazard-free patterns for fine-delay fault testing," in Proc. Int. Test Conf., 2004, pp. 213-222.
11. V. S. Iyengar, B. K. Rosen, and I. Spillinger, "Delay test generation: I. Concepts and coverage metrics," in Proc. Int. Test Conf., 1988, pp. 857-866.
12. V. S. Iyengar, B. K. Rosen, and J. A. Waicukauski, "On computing the sizes of detected delay faults," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 3, pp. 299-312, Mar. 1990.
13. B. Koenemann et al., "Delay test: The next frontier for LSSD test systems," in Proc. IEEE Int. Test Conf., 1992, pp. 578-587.
14. A. K. Pramanick and S. M. Reddy, "On the computation of the ranges of detected delay fault sizes," in Dig. Tech. Papers IEEE Int. Conf. Comput.-Aided Des. (ICCAD-89), 1989, pp. 126-129.
15. _, "On the fault coverage of delay fault detecting tests," in Proc. Eur. Des. Autom. Conf. (EDAC), 1990, pp. 334-338.
16. _, "On the fault coverage of gate delay fault detecting tests," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 1, pp. 78-94, Jan. 1997.
17. Cadence Inc., San Jose, CA, "Cadence encounter test," Aug. 2005, Product Datasheet.
18. C. Barnhart, "Delay testing for nanometer chips: New failure modes and models require new ways of testing ICs," Chip Des. Mag., pp. 8-14, Aug./Sep. 2004.
19. H. Yan and A. D. Singh, "Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die," in Proc. Int. Test Conf., 2003, pp. 105-111.
20. J. Saxena, K. Butler, V. Jayaram, S. Kundu, N. Arvind, P. Sreeprakash, and M. Hachinger, "A case study of IR-drop in structured at-speed testing," in Proc. Int. Test Conf., 2003, pp. 1098-1104.
21. W. Daasch, K. Cota, J. McNames, and R. Madge, "Neighbor selection for variance reduction in IDDQ and other parametric data," in Proc. Int. Test Conf., 2001, pp. 92-100.
22. H. Yan and A. D. Singh, "Reduce yield loss in delay defect detection in slack interval," in Proc. Asian Test Symp., 2004, pp. 372-377.
23. B. Davis, The Economics of Automatic Testing. London, U.K.: McGraw-Hill, 1982.